Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-20
2002-12-31
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S637000, C438S259000
Reexamination Certificate
active
06500713
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor manufacture, and more particularly, to the formation of metal oxide nitride oxide (MONOS) cells.
BACKGROUND OF THE INVENTION
FIG. 1
, to which reference is made, illustrates a typical prior art MONOS cell. This cell includes a substrate
10
in which are implanted a data source
12
and a drain
14
and on top of which lies an oxide-nitride-oxide (ONO) structure
16
having a layer of nitride
17
sandwiched between two oxide layers
18
and
20
. On top of the ONO structure
16
lies a gate conductor
22
. Between source
12
and drain
14
is a channel
15
formed under the ONO structure
16
. Nitride section
17
provides the charge retention mechanism for programming the memory cell. Specifically, when programming voltages are provided to source
12
, drain
14
and gate conductor
22
, electrons flow toward drain
14
. According to the hot electron injection phenomenon, some hot electrons penetrate through the lower section of silicon oxide
18
, especially if section
18
is thin, and are then collected in nitride section
17
. As is known in the art, nitride section
17
retains the received charge labeled
24
, in a concentrated area adjacent drain
14
. Concentrated charge
24
significantly raises the threshold of the portion of the channel of the memory cell under charge
24
to be higher than the threshold of the remaining portion of the channel
15
.
When concentrated charge
24
is present (i.e., the cell is programmed), the raised threshold of the cell does not permit the cell to be placed into a conductive state during reading of the cell. If concentrated charge
24
is not present, the read voltage on gate conductor
22
can overcome a much lower threshold and accordingly, channel
15
becomes inverted and hence, conductive.
One of the problems in such a MONOS cell produced by the methodology of the prior art is the damage done to the ONO region during the bit line implantation. As depicted in
FIG. 2
, a bit line
26
has been formed in the substrate
10
by implantation of dopants through the ONO structure
16
. The dopants, such as arsenic, may be implanted prior to the formation of a control gate layer
28
over the ONO structure
16
.
The implantation procedure creates a damaged area
30
in the ONO structure
16
. The damaged ONO structure immediately above the buried bit line
26
causes leakage between the buried bit line
26
and the control gate
28
, which acts as the word line. A conventional thermal anneal may be attempted in order to repair the implantation damage, but such thermal anneals typically require preclean steps which add to the expense of manufacture. Also, such a thermal annealing process will drive the arsenic bit line implant undesirably.
SUMMARY OF THE INVENTION
There is a need for a method of repairing the damage caused by arsenic bit line implants during the creation of MONOS devices, in a manner that avoids extra precleaning steps and undesirable driving of the arsenic bit line implants.
These and other needs are met by embodiments of the present invention which provide a method of forming a MONOS device, comprising the steps of forming a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer on a substrate, and implanting dopants into the substrate to form a bit line in the substrate. The charge trapping dielectric layer over the bit line is laser thermal annealed, followed by forming a control gate over the charge trapping dielectric layer.
The use of laser thermal annealing provides a precision process to anneal the charge trapping dielectric layer and repair the damage caused by the bit line implant. This is accomplished without thermal cycles that drive the arsenic bit line implant, and also do not require precleaning steps.
The other stated needs are also met by embodiments of the present invention which provide a method of creating a semiconductor device with a buried bit line, and comprises the steps of forming a charge trapping dielectric layer on a substrate, and forming a buried bit line by implanting dopants through the charge trapping dielectric layer into the substrate, thereby damaging the charge trapping dielectric layer. The damage to the charge trapping dielectric layer is repaired by a laser thermal annealing of the charge trapping dielectric layer.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4181538 (1980-01-01), Narayan et al.
patent: 6297096 (2001-10-01), Boaz
patent: 6346442 (2002-02-01), Aloni et al.
patent: 6361874 (2002-03-01), Yu
Halliyal Arvind
Ramsbey Mark T.
Tripsas Nicholas H.
Advanced Micro Devices , Inc.
Le Dung Anh
Nelms David
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