Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-03-19
2009-10-13
Dang, Phuc T (Department: 2892)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S555000, C438S614000, C257SE23021, C257SE23169
Reexamination Certificate
active
07601627
ABSTRACT:
A method for reduction of soft error rates in integrated circuits. The method including: providing a test device, the test device comprising: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level on a top surface of the substrate; selecting an energy of alpha particles of a given energy to be stopped from penetrating through the stack of one or more wiring levels; bombarding the semiconductor substrate with a flux of the alpha particles of the selected energy; and determining a combination of a thickness of a blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of the maximum energy striking a top surface of the blocking layer from penetrating through the stack of one or more wiring levels.
REFERENCES:
patent: 2005/0186326 (2005-08-01), Baumann
patent: 2006/0150128 (2006-07-01), Zhu et al.
Cabral, Jr. Cyril
Gordon Michael S.
Rodbell Kenneth P.
Dang Phuc T
International Business Machines - Corporation
Schmeiser Olsen & Watts
Trepp Robert M.
LandOfFree
Method for reduction of soft error rates in integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reduction of soft error rates in integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reduction of soft error rates in integrated circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4070016