Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2005-10-25
2005-10-25
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S759000
Reexamination Certificate
active
06958545
ABSTRACT:
A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.
REFERENCES:
patent: 5557533 (1996-09-01), Koford et al.
patent: 6550049 (2003-04-01), Torii
Gandham Rama Gopal
Kotecha Pooja M.
Matheny Adam P.
Puri Ruchir
Trevillyan Louise H.
International Business Machines - Corporation
Nelms David
Nguyen Thinh T
Schnurmann H. Daniel
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