Method for reducing the resistance of self-aligned contacts, for

Details Method for reducing the resistance of self-aligned contacts, for Method for reducing the resistance of self-aligned contacts, for

1997-01-15

1998-08-18

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438664, H01L 2144

Patent

active

057958270

ABSTRACT:
A process for fabricating MOSFET devices, for a SRAM cell, using a polycide contact structure, self-aligned to an underlying source and drain region, has been developed. This process features the use of a high temperature, rapid thermal anneal step, used to dissolve native oxide at the polycide-source and drain interface, thus reducing the resistance at the interface of the polycide self-aligned structure, and the underlying source and drain area.

REFERENCES:
patent: 5461006 (1995-10-01), Mehra
patent: 5510296 (1996-04-01), Yen et al.
patent: 5541137 (1996-07-01), Manning et al.
patent: 5581114 (1996-12-01), Bashir et al.

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