Method for reducing the capacitance across the layer of tunnel o

Details Method for reducing the capacitance across the layer of tunnel o Method for reducing the capacitance across the layer of tunnel o

1998-10-28

2000-05-16

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438264, H01L 218247

Patent

active

06063667&

ABSTRACT:
The capacitance across the layer of tunnel oxide in an electrically-erasable programmable read-only-memory (EEPROM) cell is reduced by forming the layer of tunnel oxide to have a first region which is substantially thicker than a second region. The thicker region of tunnel oxide results from doping the buried region exposed by the tunnel window so that the buried region has different levels of dopant concentration. When the tunnel oxide is then grown over the buried region, the oxide formed over the more heavily doped portion grows at a faster rate than does the portion with the lower dopant concentration.

REFERENCES:
patent: 4823175 (1989-04-01), Fontana
patent: 5215934 (1993-06-01), Tzeng
patent: 5585656 (1996-12-01), Hsue et al.
patent: 5814543 (1998-09-01), Nishimoto et al.
patent: 5863822 (1999-01-01), Kanamori et al.
Kolodny, A. et al., "Analysis and Modeling of Floating-Gate EEPROM Cells," pp. 128-129 [Reprinted from IEEE Trans. Electron Devices, vol. ED-33, No. 6, pp. 835-844, Jun. 1986].

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