Method for reducing stress on collimator titanium nitride layer

Details Method for reducing stress on collimator titanium nitride layer Method for reducing stress on collimator titanium nitride layer

1997-09-30

2000-09-19

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438637, 438643, 438644, 438648, 438653, 438654, 438656, 438680, 438685, 438785, H01L 214763

Patent

active

06121132&

ABSTRACT:
A method for reducing the stress on a titanium nitride layer formed by collimator sputtering. On a semiconductor substrate, an insulated oxide layer is formed. A trench is formed in the insulated oxide layer. On the trench, a first titanium nitride layer is formed conformally by using physical or chemical vapor deposition as a buffer layer. A second titanium nitride layer is formed by collimator sputtering on the first titanium layer. The orientation of lattice arrangement of the second titanium nitride layers is changed from <100>-orientation to <111>-orientation, and therefore, the stress is reduced.

REFERENCES:
patent: 5627102 (1997-05-01), Shinriki et al.
patent: 5763948 (1998-06-01), Sumi

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