Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1998-01-06
1999-08-17
Hiteshew, Felisa
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438700, 438710, 438714, H01L 213065, H01L 21336
Patent
active
059393351
ABSTRACT:
The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
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Arndt Kenneth C.
Conti Richard A.
Dobuzinsky David M.
Economikos Laertis
Gambino Jeffrey P.
Capella Steven
Champagne Donald L.
Hiteshew Felisa
International Business Machines - Corporation
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