Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-04-15
2001-02-27
Clark, Sheila V. (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S697000
Reexamination Certificate
active
06194313
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods.
Background: Metal Plugs
In modern integrated circuit fabrication, it is increasingly necessary to fill vias and contact holes which have a high “aspect ratio”. This means a ratio of height to width which is 2:1 or more, and, as technology progresses, may be as high as 10:1 or more in future generations. Completely filling such holes with metal at an acceptably low temperature is very difficult, particularly for metals (such as aluminum) which do not have a good low-temperature chemical vapor deposition (CVD) process.
One concern with aluminum metallization is electromigration: a pure aluminum line may gradually thin out, in service, in locations of high current density. However, the addition of copper greatly reduces this tendency. Longer electromigration (EM) lifetimes improve the product reliability. Thus, typical aluminum alloys use silicon (typically one-half to one percent atomic) or copper (typically one-half to one percent atomic) or both as alloying agents. Efforts have been made to find other satisfactory aluminum alloy compositions; see e.g. Kikuta and Kikkawa, “Electromigration characteristics for Al—Ge—Cu,” 143 J. Electrochem. Soc. 1088 (1996), which is hereby incorporated by reference.
In a typical plug process, as shown in prior art
FIG. 3A
, a contact or via hole
302
is etched through a dielectric layer
310
to expose an underlying layer
300
, followed by the filling of the cavities
302
with a metal layer (e.g. tungsten, aluminum, or copper) and the etchback of the metal layer to remove it from on top of the dielectric
310
to leave metal plugs
320
.
The etchback process for the metal plug fill can cause an appreciable amount of plug recess
325
, as can be seen in FIG.
3
A. This can create problems after the subsequent deposition of the metal film stack
330
(e.g. two titanium nitride layers separated by a layer of aluminum) over the via/contact plugs
320
. For example, the following problems can occur when forming overlying via structures: via etch stopping, shown in prior art
FIG. 3B
, which is due to an excessive amount of HSQ (Hydrogen Silsesquioxane)
360
(or any carbon or fluorine containing organic polymer) in the vias
370
as a result of non-planarity arising from the plug recess
325
; and via poisoning, shown in prior art
FIG. 3C
, which is due to the outgassing of SOG (spin-on glass)
360
during deposition of aluminum
380
resulting in poor step coverage of the aluminum
380
.
Background: Planarization
One conventional approach to the problem of plug recess includes performing a chemical-mechanical polishing process on the metal plugs after deposition. Chemical-mechanical polishing (CMP) is a planarization technique which has become increasingly important in integrated circuit processing in the 1990s. CMP, unlike most other planarization techniques, provides global planarization. This global planarization avoids problems of step coverage, and hence helps achieve the numerous multiple layers of metallization which are now desired. Global planarization also improves lithographic resolution, by removing constraints on the depth of field.
In a CMP process, a wafer is polished in a slurry of a very fine abrasive (typically alumina or silica). The slurry has a chemical composition which accelerates removal of the top surface. For example, for removal of tungsten, an acidic and oxidizing slurry is used. This helps to convert the surface of the tungsten into a tungsten oxide, which is easily removed by the mechanical polishing operation. For removal of dielectrics, a basic chemistry is more typically used, which is discussed in DeJule et al., “Advances in CMP,” SEMCONDUCTOR INTERNATIONAL, p.88-96 (November 1996), which is hereby incorporated by reference. In order to produce a completely planar surface, one conventional approach uses a two-step CMP process, in which a short oxide CMP step follows a metal CMP step. This approach is described in U.S. Provisional patent application, Ser. No. 60/033,293, filed Dec. 10, 1996, which is hereby incorporated by reference.
Another conventional planarization technique involves using a photoresist to etchback the material. This process is carried out by first depositing the CVD film that will serve as the interlevel dielectric. This layer is then coated with a photoresist film that will later be etched off non-selectively. Planarization of the dielectric surface occurs by controlling the difference in plasma etch rates between the photoresist and the dielectric. However, this planarization process is completely non-selective and can result in overetching of the dielectric.
Methods for Reducing the Recess
The present application discloses structures and methods to reduce the effective recess in metal plugs by performing either a dielectric etch step, selective to the metal in question, after a metal CMP, or a dielectric etch or CMP step after a metal etch. The disclosed methods can be used for any metal plug (e.g. Aluminum, tungsten, copper etc.). In addition, this method is also applicable in contact, via, and trench applications. Furthermore, this process can advantageously be used in logic, SRAM, and DRAM applications. The recess height can even be made negative (so that the plug protrudes above the dielectric), which has further advantages.
Advantages of the disclosed methods and structures include:
lower cost;
manufacturable;
no need for new hardware development;
reduced recess;
reduced chance of via etch stop;
less chance of via poisoning; and
reduced dielectric roughness.
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Dixit Girish Anant
Hsu Wei-Yung
Singh Abha R.
Xing Guoqiang
Brady III Wade James
Clark Sheila V.
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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