Method for reducing poly-depletion in dual gate CMOS...

Details Method for reducing poly-depletion in dual gate CMOS... Method for reducing poly-depletion in dual gate CMOS...

2006-02-28

2010-02-16

Chen, Jack (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S221000, C257SE21001

Reexamination Certificate

active

07662684

ABSTRACT:
Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical principles. First, the doping efficiency is increased when the dose of N+ ion implantation is increased. Second, the doping efficiency is increased when the thickness of N+ polysilicon is reduced. Third, the increase of depletion caused by the reduction of the channel width is inhibited when the EFH is adjusted to be less than 0. Fourth, the overall doping efficiency is increased when each step of polysilicon deposition and ion implantation is divided into multiple steps.

REFERENCES:
patent: 6800512 (2004-10-01), Itonaga et al.
Chang-Hoon Choi, et al; “Gate Length Dependent Polysilicon Depletion Effects” IEEE Electron Device Letters, vol. 23, No. 4, Apr. 2002, pp. 224-226.
Youngmin Kim, et al; “Trench Isolation Step-Induced (TRISI) Narrow Width Effect on MOSFET”, IEEE Electron Device Letters, vol. 23, No. 10, Oct. 2002, pp. 600-602.

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