Method for reducing poly-depletion due to thickness...

Details Method for reducing poly-depletion due to thickness... Method for reducing poly-depletion due to thickness...

2006-06-27

2006-06-27

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S218000

Reexamination Certificate

active

07067367

ABSTRACT:
Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical principles. First, the doping efficiency is increased when the dose of N+ ion implantation is increased. Second, the doping efficiency is increased when the thickness of N+ polysilicon is reduced. Third, the increase of depletion caused by the reduction of the channel width is inhibited when the EFH is adjusted to be less than 0. Fourth, the overall doping efficiency is increased when each step of polysilicon deposition and ion implantation is divided into multiple steps.

REFERENCES:
patent: 6573575 (2003-06-01), Yamazaki
patent: 6800512 (2004-10-01), Itonaga et al.

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