Method for reducing overlap capacitance in field effect...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S305000, C438S595000, C438S700000, C438S705000, C257S340000, C257S387000, C257S408000, C257SE29268, C257SE29269, C257SE21634

Reexamination Certificate

active

07824989

ABSTRACT:
A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain region, the drain region having a drain extension that overlaps and extends under the gate conductor at selected locations along the width of the gate; and the drain region further comprising a plurality of recessed areas corresponding to areas where the drain extension does not overlap and extend under the gate conductor, wherein the plurality of recessed areas is formed only in the drain region.

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patent: 4-208528 (1992-07-01), None

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