Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
Reexamination Certificate
1997-06-19
2001-04-17
Beck, Shrive (Department: 1762)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
C438S763000, C438S788000, C438S910000, C427S569000, C427S579000
Reexamination Certificate
active
06218218
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates, in general, to an improved method for reducing the problems caused by electrostatic charging during the wafer manufacturing process, and in particular, to a method that reduces the failure of gate oxides created when charges within a wafer cause damage to the gate oxide during a subsequent polysilicon deposition process.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in connection with MOS technologies, as an example.
As MOS technology advances, increasingly thinner gate oxide layers are required. With thinner layers comes an increased demand for improved efficiency, decreased failure rates, and greater control over the process. One problem that is widely recognized in the wafer manufacturing process is gate oxide charging. Several steps in the process have been implicated in the charging process, including: ion implantation, ashing, surface scrubbing, and etching.
Gate oxide damage may also occur during the subsequent deposition of an oxide layer. For example, damage due to a plasma enhanced TEOS or silicate deposition, leading to degradation in hot carrier lifetime, has been reported to vary with the thickness of the oxide layer deposited. Gate oxide damage has been shown to be reduced by a protective layer of polysilicon with a thickness of 150 nm. The 150 nm polysilicon layer was reported to block charging effects during subsequent processing.
The conventional theory of plasma-charging damage, on the other hand, relies strongly on the antenna's ability to collect charges from the plasma. In contrast, a process known as “photoconduction” has been proposed as a mechanism for charging damage that increases as the thickness of the deposition film increases.
Both theories, however, fail to explain the continuously increasing damage as more dielectric is deposited. The failure of the photoconduction theory is particularly true since even a thin layer of dielectric can prevent the antennae from further charging.
Alternatively, others have proposed that the correlation between charging and oxide deposition indicates that the thickness of the layer causes a “photocurrent” to fall off quickly as the inverse square of the distance that the photons have to travel. In the vertical direction, the fall off would be even faster because less photons would penetrate the thickness of the oxide.
Therefore, the current understanding in the field is that thickness dependent damage and the effect of saturation is a combination of the photocurrent fall off and damage saturation, whether the photocurrent does or does not fall off. Furthermore, the photocurrent fall off would also make the photoconductive effect a very local phenomenon.
SUMMARY OF THE INVENTION
It has been found that gate oxide charging during the wafer manufacturing process leads to high failure rates. The need for eliminating gate oxide failure caused by wafer charging has become increasingly important because gate oxide layers are being made thinner and thinner. What is needed, therefore, is a method of plasma enhanced oxide deposition that prevents circuit failure caused by charging effects.
The present invention provides a method of eliminating the conditions that cause gate oxide damage during the post polysilicon gate oxide deposition. In this regard, the present invention comprises maintaining the internal pressure within a production line chamber until the power level within the chamber drops below a specified level. Maintaining the pressure within the plasma enhanced production line during power down remedies the impact of charging, which otherwise creates catastrophic damage impacting on the reliability of the oxide. Furthermore, the present invention reduces the gate oxide damage that occurs during oxide deposition, which is caused by inefficient lateral discharging of the layer following deposition of the polysilicon layer.
Although a variety of assembly lines have been used in the art, the invention can be used to solve a problem common to all like-production assembly lines. The present invention can be used with all like-production assembly lines, as they are programmed by the manufacturer to reduce the pressure within the production line chamber following the TEOS deposition step, also known as the power lift step. The post oxide deposition step is used to release the wafer from the electrostatic charging that occurs during the wafer manufacturing process.
Another aspect of the present invention is to allow for continued use of any of the processing gases used in the art of plasma deposition. The present invention can use a production line chamber processing gas such as TEOS gas, during the creation of the gate oxide assembly. Other gases, such as silane, may also be used with the present invention.
The present invention solves the failure rate caused by charging during the manufacturing of wafers and improves the gate oxide quality of finished products. The present invention was used to discover the mechanism of charging, mainly the drop in pressure during the post oxide deposition step.
These and other features of the invention that will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.
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Adams Mary C.
Jenkins Ingrid G.
Malone Farris D.
Salamati-Saradh Sima
Wyke David R.
Beck Shrive
Brady III Wade James
Chen Bret
Garner Jacqueline J.
Telecky , Jr. Frederick J.
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