Method for reducing dimensions between patterns on a...

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S751000, C257SE21215, C257SE21316

Reexamination Certificate

active

10465850

ABSTRACT:
A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.

REFERENCES:
patent: 6669858 (2003-12-01), Bjorkman et al.
patent: 6750150 (2004-06-01), Chung et al.
patent: 6770567 (2004-08-01), Ko et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for reducing dimensions between patterns on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for reducing dimensions between patterns on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing dimensions between patterns on a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3838069

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.