Method for reducing dimensions between patterns on a...

Details Method for reducing dimensions between patterns on a... Method for reducing dimensions between patterns on a...

2007-12-04

2007-12-04

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S751000, C257SE21215, C257SE21316

Reexamination Certificate

active

10465850

ABSTRACT:
A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.

REFERENCES:
patent: 6669858 (2003-12-01), Bjorkman et al.
patent: 6750150 (2004-06-01), Chung et al.
patent: 6770567 (2004-08-01), Ko et al.

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