Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-03-04
2011-10-18
Sandvik, Benjamin (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21642
Reexamination Certificate
active
08039338
ABSTRACT:
By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
REFERENCES:
patent: 5147499 (1992-09-01), Szwejkowski et al.
patent: 5550079 (1996-08-01), Lin
patent: 5885861 (1999-03-01), Gardner et al.
patent: 6110818 (2000-08-01), Haskell
patent: 6342438 (2002-01-01), Yu et al.
patent: 6373112 (2002-04-01), Murthy et al.
patent: 6566181 (2003-05-01), Bevk
patent: 7303952 (2007-12-01), Adkisson et al.
patent: 2002/0072182 (2002-06-01), Ha et al.
patent: 2004/0036119 (2004-02-01), Tang et al.
patent: 2005/0282386 (2005-12-01), Yoshimura
patent: 2006/0073689 (2006-04-01), Adkisson et al.
patent: 2008/0157215 (2008-07-01), Miyashita
patent: 19750340 (1999-06-01), None
patent: 08031931 (1996-02-01), None
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 021 563.5 dated Dec. 16, 2008.
“Surface Cleaning and Wet Processing Terminology,” Contributions by Motorola Corporation, 1999 Arizona Board of Regents for The University of Arizona.
PCT Search Report and Written Opinion from PCT/US2009/002669 dated Jun. 26, 2009.
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 021 563.5 dated Jun. 22, 2011.
Horstmann Manfred
Javorka Peter
Ruttloff Kerstin
Wieczorek Karsten
GLOBALFOUNDRIES Inc.
Sandvik Benjamin
Williams Morgan & Amerson P.C.
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