Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-11-06
2004-09-14
Guerrerro, Maria (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S694000, C438S710000, C438S906000, C438S913000, C438S974000
Reexamination Certificate
active
06790777
ABSTRACT:
TECHNICAL FIELD OF INVENTION
The present invention relates generally to fabrication of semiconductor devices, and more particularly to reducing contamination, electromigration, and corrosion of conductive material during fabrication thereof.
BACKGROUND OF THE INVENTION
Integrated circuits fabricated on semiconductor substrates for Ultra Large Scale Integration (ULSI) require multiple levels of conductive interconnections for electrically connecting the discrete semiconductor devices that comprise the circuits. Conventionally, the multiple levels of interconnections are separated by layers of insulating material. These interposed insulating layers typically have etched via holes which are used to electrically connect one level of metal to another. Typically, the conductive interconnection material is aluminum, titanium, tungsten or tantalum. As device dimensions decrease and device densities increase, however, conductive materials having lower resistivity, such as copper, are employed.
One well-known method for creating integrated circuits such as those described above is by chemical vapor deposition (CVD). Typically, a precursor gas is mixed with a carrier gas and introduced to a deposition chamber at an elevated temperature. Upon contact with a substrate (e.g., a semiconductor wafer) within the chamber, the precursor gas decomposes into various elements and reacts with the surface to create the desired material (e.g., an insulative layer such as an oxide, or conductive material such as copper). Such processes may also be enhanced by the use of a plasma within the chamber which provides for a more uniform deposition process, for example, when filling an opening in an oxide layer with conductive material. However, deficiencies in the CVD process may create undesirable results. It has been found typically that between the time that a conductive material is deposited upon the substrate and an insulative or barrier layer is deposited over the conductive material, the conductive material is subjected to an oxidation reduction reaction. For example, the topmost exposed surface of a copper interconnect is reduced to copper oxide. Such surface oxides inhibit the adhesion of further material layers (e.g., an insulative layer such as a nitride layer) that are deposited thereover.
One particular method known in the art for removing native oxides from conductive interconnects is by chemical removal of the native oxide. One conventional method for chemically removing an oxide from a copper layer is illustrated in
FIG. 1
, and includes the use of a hydrogen-based plasma. According to the conventional method
100
, a semiconductor substrate is inserted into a process chamber at a predetermined temperature at
105
. Chemically-reactive oxide-reducing gases such as ammonia (NH
3
) or hydrogen (H
2
) are then introduced into the process chamber at
110
, and an oxide-reducing plasma is initiated by an application of a first RF power to the hydrogen-based oxide-reducing gases at
115
. The oxide-reducing plasma chemically reacts with the oxide, and reduces the oxide to form copper (Cu) and byproducts (e.g., water (H
2
O) and hydroxide (OH)). These byproducts are then pumped out of the process chamber.
Nitride-forming gases, such as a mixture of silane (SiH
4
), ammonia (NH
3
) and nitrogen (N
2
), are subsequently introduced into the same process chamber at
120
, and the first RF power is changed to a suitable second RF power at
125
, thereby forming a second plasma suitable for CVD of a nitride layer over the copper. Following the formation of the nitride layer, the substrate is removed from the process chamber at
130
.
Unfortunately, the conventional method
100
has several disadvantages. For example, adhesion of the nitride layer to the copper layer is adversely affected during this process because the silane may react with residual water or hydroxide that was not evacuated from the chamber. Such a reaction causes an undesirable hazy film to form over the conductive interconnect, thereby decreasing adhesion of the nitride layer to the underlying copper. Furthermore, a processing temperature in the chamber typically remains substantially constant, wherein hillock growth in the copper layer is accentuated by reducing the copper oxide at a temperature typically suited to the nitride deposition, thereby causing further undesirable effects in later depositions. Additionally, the copper and silane thermally react to form copper silicides (CuSi
x
) when the plasma is turned off in preparation for subsequent process steps. Either of these films are undesirable for further depositions. Furthermore, modifying the RF power at
125
appears to induce plasma damage and antenna damage, and has deleterious effects on gate oxide integrity (GOI).
Therefore, there is a need in the art for a method of semiconductor device construction that reduces the amount of native oxide formation on the conductive material used to form the device, wherein the method mitigates the deleterious effects associated with conventional techniques.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to improving an interface of a semiconductor substrate, and more specifically to a method of reducing an oxide formed over a metal layer and depositing a dielectric layer over said metal layer. The metal layer, for example, comprises a copper layer, wherein a native copper oxide is formed by oxidation of the metal layer. The dielectric layer, for example, comprises a nitride layer which is formed over the copper metal layer.
According to one exemplary aspect of the present invention, a method for improving an interface is provided, wherein two or more semiconductor substrates such as silicon wafers are provided, whereon a first layer has been formed. The first layer, for example, comprises a metal layer such as copper, wherein the first layer furthermore comprises an oxidized region. A first and second semiconductor substrate are consecutively inserted into a first process chamber, such as a plasma-enhanced chemical vapor deposition (PECVD) chamber, when the first process chamber is in a first loading position. A first processing position is then established, wherein the first and second substrates are processed. The first and second substrates are generally simultaneously subjected to a first temperature for a first predetermined period of time. The first and second substrates, for example, are placed on a first heated disk, wherein the substrates are subjected to the first temperature for a first soak time.
After the first soak time has generally elapsed, a first plasma is subsequently introduced into the first process chamber, wherein the first plasma is energized by a first predetermined power for a second predetermined period of time, thereby generally simultaneously chemically reducing the oxidized region of the first layer on the first and second substrates. The first loading position is then established again, and the first and second substrates are consecutively removed from the first process chamber.
According to one exemplary aspect of the present invention, prior to removing the first and second substrates from the first process chamber, a third and fourth substrate are consecutively inserted into the first process chamber when the first process chamber is in the first loading position, and the first processing position is again established. The first, second, third, and fourth substrates are then simultaneously processed in a manner similar to the previous processing of the first and second substrates, wherein the first and second substrates are proc
Brugler Mercer Lusk
Hartwig Sarah
Ruan Ju-Ai
Tessmer Glenn J.
Garner Jacqueline J.
Guerrerro Maria
LandOfFree
Method for reducing contamination, copper reduction, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing contamination, copper reduction, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing contamination, copper reduction, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3238344