Method for reducing chip warpage

Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure

Reexamination Certificate

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C438S126000

Reexamination Certificate

active

08053336

ABSTRACT:
A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

REFERENCES:
patent: 5650881 (1997-07-01), Hornbeck
patent: 6568794 (2003-05-01), Yamanaka et al.
patent: 7167298 (2007-01-01), Pan
patent: 7307777 (2007-12-01), Pan
patent: 2010/0032767 (2010-02-01), Chapman et al.
patent: 523905 (1976-10-01), None

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