Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1998-05-11
1999-11-16
Utech, Benjamin
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438702, 438706, 438720, H01L 2100
Patent
active
059857650
ABSTRACT:
A method for reducing bonding pad loss is achieved using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to provide external electrical connections for I/Os and power. And fuses are used in the underlying insulating layers to remove redundant defective circuit elements and thereby repair defective chips. It is desirable (cost effective) to etch the contact openings in the passivation layer to the bonding pads near the top surface on the chip and to concurrently etch the much deeper fuse openings in the thick underlying insulating layers over the fuses. However, because of the difference in etch depth of the two types of openings, the bonding pads composed of Al/Cu are generally overetched causing bond-pad reliability problems. This invention uses a novel process in which a capping layer, having a low etch rate, is formed on the bonding pads to prevent overetching while the fuse openings are etched to the desired depth in the thicker insulating layers.
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Hsiao Yung-Kuan
Lee Yu-Hua
Wu Cheng-Ming
Ackerman Stephen B.
Chen Kin-Chan
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
Utech Benjamin
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