Method for reduced electrical fusing time

Data processing: measuring – calibrating – or testing – Testing system – Of circuit

Reexamination Certificate

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C714S726000

Reexamination Certificate

active

07089136

ABSTRACT:
An electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output of the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain when the next fuse(s) is not to be blown. Accordingly, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.

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Ouellette et al., “Shared fuse macro for multiple embedded memory with redundancy”, May 2001, Custom Integrated Circuits, pp. 191-194.
Cowan et al., “On-chip repair and an ATE independent fusing methodology”, Oct. 2002, Test Conference, pp. 178-186.

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