Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2002-12-19
2004-02-17
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S756000, C438S771000, C438S787000
Reexamination Certificate
active
06693047
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor wafer manufacturing of multi-layered semiconductor structures and more particularly to a method for recycling the semiconductor process wafer including carbon-doped low-k dielectric layers.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring have increasingly required the use of low-k (low dielectric constant) dielectric insulating layers to increase signal transport speeds as device sizes have decreased.
Typical low-k materials in use have included carbon doped oxides (e.g., silicon dioxide) using commercially available precursors and processes such as SiLK™ and BLACK DIAMOND™ processes. Such carbon doped oxides are also known as organo-silicate glasses (OSG) formed by chemical vapor deposition (CVD) processes from organo-silane and organo-siloxane precursors. CVD carbon doped oxide low-k dielectrics typically consist of a porous and low density material to thereby reduce the overall dielectric constant, for example, less than about 3.2. Carbon doped oxides are used in a variety of semiconductor structures, typically by forming multiple layers of the carbon doped oxides within which other semiconductor structures such as metal interconnect lines are formed. For example, carbon doped oxides may be used as dielectric insulting layers also known as inter-metal dielectric (IMD) layers, thin films of capping layers or as a filling material for certain structures.
Frequently, for various reasons, a semiconductor wafer, for example a silicon semiconductor wafer forming the process wafer base for forming devices, is recycled following the unacceptable processing of overlying layers in a multi-layer semiconductor device manufacturing process. Any number of processing problems may occur, for example, with deposition of the carbon doped oxide or other problems with other processes used to create device features. A number of quality control testing methods are preformed following selected processing steps generally referred to as wafer acceptance testing (WAT) where the acceptability of the semiconductor process wafer may be rejected and ‘scrapped’ for various reasons resulting in a significant non-productive cost.
The prior art practice has been to send the rejected or scrapped process wafers to wafer suppliers for processing where the dielectric layers including carbon doped oxide layers are removed to allow the semiconductor wafer base to be reused. The prior art practice to remove carbon doped oxide layers has been to use a wafer polishing process including chemical and mechanical methods to remove the various dielectric layers overlying the base semiconductor wafer. Following removal of dielectric layers and other features overlying the semiconductor wafer, the semiconductor wafer is recycled or reused for a new multi-layer semiconductor device manufacturing process. The prior art practice has been to provide the scrapped process wafers to an outside party for recycling as the batch wafer polishing processes are not compatible with device manufacturing tools or processes. As semiconductor wafer manufacturing move to larger diameter wafers, for example 12 inch wafers, the cost of scrapping or recycling a process wafer will increase.
There is therefore a need in the semiconductor manufacturing to art to develop a process whereby dielectric layers including carbon doped oxide layers may be removed from rejected semiconductor wafers for recycling that can be performed in-house and is compatible with existing manufacturing processes.
It is therefore an object of the invention to a process whereby dielectric layers including carbon doped oxide layers may be removed from rejected semiconductor wafers for recycling that can be performed in-house and is compatible with existing manufacturing processes while overcoming other shortcomings and deficiencies in the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for removing at least one carbon doped oxide layer over a surface to recycle the semiconductor process wafer.
In a first embodiment the method includes providing a semiconductor wafer including a process surface including at least one carbon doped silicon oxide layer; oxidizing the carbon doped oxide layer according to an oxidizing treatment to convert at oxidize at least a portion of the carbon doped oxide layer to produce silicon oxide; and, wet etching the silicon oxide to substantially remove the silicon oxide.
These and other embodiments, aspects and features of the invention will become better understood from a detailed description of the preferred embodiments of the invention which are described in conjunction with the accompanying drawings.
REFERENCES:
patent: 6168726 (2001-01-01), Li et al.
patent: 6346490 (2002-02-01), Catabay et al.
patent: 6407013 (2002-06-01), Li et al.
patent: 6486061 (2002-11-01), Xia et al.
patent: 6562700 (2003-05-01), Gu et al.
patent: 2003/0032305 (2003-02-01), Yau et al.
Chang Wen
Jeng Syun-Ming
Lu Chih-Cheng
Ghyka Alexander
Taiwan Semiconductor Manufacturing Co. Ltd.
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