Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-12-02
2004-12-28
Clark, S. V. (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C257S751000
Reexamination Certificate
active
06835657
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to methods for recrystallizing metal in features of a semiconductor chip as part of a global planarization stepduring the manufacture of the chip, which by the method of recrystallization, also enhances the electromigration resistance of the film as well as alleviates the resistivity increase of metal lines in the regime below 200 nm due to grain boundary scattering and other interfacial effects.
BACKGROUND OF THE INVENTION
The development of ultra-large-scale integration (ULSI) requires higher integration density with smaller design rules. Aluminum alloys have been widely used as metallization materials, but for ultra-large scale integration (ULSI) (e.g., the use of integrated circuits with more than a million logic gates), they are susceptible to electromigration and stress migration. The device performance has also become limited by the RC delay associated with aluminum alloy interconnects. An example of a multilayer ULSI application is illustrated in FIG.
7
. In
FIG. 7
, features such as vias
710
and
712
connect one or more interconnect layers
702
.
As ULSI technology progresses, the feature size (e.g. size of interconnects, vias, contacts) decreases while chip size increases. The lengths of features also increase, leading to higher resistances. The distance between adjacent features lessens. The capacitance between the adjacent features, therefore, increases although the capacitance between the feature and the ground substrate decreases, resulting in an increase in the total feature capacitance in the submicron range. Since both line resistance, R, and the capacitance associated with the dielectric, C, contribute to the interconnect delay, the total interconnect delay increases rapidly as the feature size decreases in the submicron range. The RC delay is given by:
RC
≈
ρ
t
M
L
2
ϵ
ILD
t
ILD
where &rgr;, L, and t
M
, are the resistivity, length and thickness of the interconnect, and ∈
ILD
and t
ILD
are the permittivity and thickness of the interlevel dielectric (ILD).
To reduce the RC delay, two approaches are used. One lowers C by adapting low permittivity (low-K) materials as interlevel dielectrics (ILD). Such materials include SiOF, SiOC, polymers, etc. The other lowers R by using interconnect materials with lower resistivity. A
1
and A
1
alloys have been used as interconnect materials for more than 30 years. Only three elements exhibit lower resistivity than aluminum: gold, silver, and copper. Among them, gold has the highest resistivity. Although silver has the lowest resistivity, it has poor electromigration reliability. Copper offers good mechanical and electrical properties. The resistivity of copper is about 40% better than that of aluminum. The self-diffusivity of copper is also the smallest among the four elements, resulting in improved reliability. Therefore, copper or copper alloys are promising materials for ULSI applications, such as the application illustrated in FIG.
7
. One advantage of using copper and/or low-K dielectric is that the required number of layers
702
(
FIG. 7
) in a ULSI application can be reduced.
There are a number of ways in which semiconductors are manufactured. Referring to
FIG. 1
a
, in a typical approach, known as the Damascene process, interlevel dielectric
102
is deposited. Next, trenches
104
are patterned by a method such as reactive ion etching (RIE). Then, optionally, a diffusion barrier
106
(
FIG. 1
b
) is deposited. Optional diffusion barrier
106
is usually needed for copper and copper alloy applications because copper and copper alloys typically have poor adhesion to typical dielectric materials. Further, typical dielectric materials are not effective barriers for copper. Thus, copper can diffuse into the dielectric materials causing a degradation in the device performance.
After the diffusion barrier
106
has been deposited, metal (e.g., copper or a copper alloy) is deposited using a metal deposition technique, such as electrochemical deposition, to form interconnects
108
(
FIG. 1
c
), vias, contacts or other features (not shown). Finally, excess copper or copper alloy (overburden
110
;
FIG. 1
c
) and barrier layers in the filled region are planarized. When overburden
110
is planarized, it becomes more even, and is no longer referred to as an overburden. Rather, it is referred to as a planarized metal surface over dielectric layer
102
. Global planarization of overburden
110
is achieved by methods such as chemical mechanical polishing (CMP). Thus, after CMP, the metal above dielectric layer
102
is removed, leaving only metal inside trenches and vias (e.g., interconnect
108
) (
FIG. 1
d
). See, for example, Murarka et al., 1993
, MRS Bulletin
18, 46-51; and Contolini et al., 1997
, Solid State Technology
40, 155-162.
Referring to
FIG. 2
, a typical ULSI application has multiple layers of interconnects
108
. Successive layers of interconnects
108
are connected by vias
202
(
FIG. 2
i
). When metal such as copper or copper alloy is used for both interconnects
108
and vias
202
, the dual Damascene process is often used to form the ULSI application. See, for example, Kaanta et al., 1991, IEEE VMIC Conf., pp. 144-52. The self-aligned dual Damascene process is illustrated in FIG.
2
. In the process, via
202
and interconnect
108
shapes are reactive ion etch patterned on interlayer dielectrics by two etching steps. Then, copper or copper alloy deposition and chemical mechanical polishing is performed only once.
Regardless of whether the single or dual Damascene process is used, the final CMP step is made more difficult because of the uneven nature of overburden
110
. In typical ULSI applications, the density of features, such as interconnects
108
and vias
202
, is not uniform. In areas of high feature density, overburden
110
is thinner than in areas where feature density is relatively sparse. As feature size is reduced, overburden
110
uneveness becomes an even larger obstacle to achieving global planarization and leads to the undesired properties of non-uniform and inconsistent metal lines resistivities during manufacturing.
Another obstacle in the use of copper or copper alloy in ULSI applications is their electromigration properties. The electromigration phenomenon occurs when the superposition of an electric field onto random thermal diffusion in a metallic solid causes a net drift of atoms in the direction of electron flow. Electromigration leads to degradation in interconnect reliability.
Still another obstacle in the use of copper and copper alloys in ULSI applications is stress migration resistance. Stress migration resistance arises due to a high degree of intrinsic stress in copper or copper alloy interconnects, vias, contacts, as well as other features created using electrochemical deposition (ECD). ECD copper grains are very small. For deposition purposes, this grain size is advantageous because it facilitates deposition into deep features in the ULSI application that have very high aspect ratios without the formation of gaps or other voids. However, the resulting fine-grained film deposition is under a high degree of intrinsic stress due to an excess of vacancies, dislocations, and other crystalline imperfections. See, for example, Ritzdorf et al, 1998, IEEE Proc. Int'l Interconnect Tech. Conf., pp. 106-108.
In some ULSI applications, there are more than 100 line segments connecting devices, each line carrying current densities as high as 0.4 mA/cm
2
. See Thompson & Lloyd, (June 1993), MRS Bulletin pp. 19-24. Compared to the maximum current density for household wiring of about 10
2
A/cm
2
, theses are significantly higher current densities. At such large current densities, electrons scatter with metal atoms, and the transferred momentum results in atomic migration. As atoms electromigrate, voids are formed at upstream and hillocks are formed at downstream of electron flow (FIG.
3
). Voids and hillocks will grow and eventually cause open circuit or short circuit failure
Applied Materials Inc.
Clark S. V.
Moser Patterson & Sheridan
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