Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of...
Reexamination Certificate
2000-10-20
2004-07-13
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Radiation or energy treatment modifying properties of...
C438S730000, C216S067000, C250S492200
Reexamination Certificate
active
06762136
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor manufacturing generally and more specifically to thermal processing of substrates used to make semiconductor devices.
BACKGROUND OF THE INVENTION
In the fabrication of different types of advanced semiconductor devices very rapid thermal processing is becoming a critical need. Device applications include diffusion and annealing of implanted semiconductors to form high conductivity structures in substrates; annealing of a number of different materials used in CMOS logic devices and DRAM memory devices as well as processing specialty compound semiconductor devices. A general requirement for many such advanced devices is to very rapidly raise the temperature of the surface and then very rapidly cool-down the surface to enable a diffusion or anneal process without degrading other characteristics of the device materials.
Application of Shallow Junction and Channel Formation in Silicon Devices
There exists a manufacturing need to form very shallow, very high conductivity structures in silicon logic and memory devices with critical pattern dimensions of 0.13 microns and below. Critical shallow high conductivity structures are used in logic devices, source and drain connection junctions and in gate channels; and in silicon junctions for memory devices. Need for a production means to make shallow, highly conductive paths in the range of 40-20 nm depth are projected by 2003. Means to produce junction and channel depths of less than 10 nm are being investigated by many.
Thermal Budget Limitation on Shallow Junction and Channel Formation
To form high conductivity shallow paths in single crystal silicon, a thermal processing step is required. The two methods of driving the doping material into the single crystal silicon so that the doped crystal becomes highly conductive are: (1) implantation of the doping material into the silicon by accelerating the doping atoms into the silicon surface with sufficient energy, followed by a high temperature anneal to repair the crystal damage by the implant process; and (2) diffusion of the doping atoms into the silicon by having a high concentration of doping material on the silicon surface and raising the silicon temperature so that the doping material-diffuses into the silicon. The seed doping material may be in a layer deposited on the silicon surface or may be in the gas at the surface of the wafer.
If shallow high conductivity paths are to be formed there is a maximum allowable “thermal budget” for a given depth of the doping material responsible for the conductivity. Two factors that relate to obtaining very high conductivity shallow structures are: diffusion rates and concentration of the doping atoms in the silicon.
The diffusion rate of a doping material into silicon follows an exponential type dependence on temperature. For a high temperature requirement (e.g., 1200° C.), the doping atoms will rapidly diffuse into the silicon and in a short time a shallow highly conductive area can be obtained.
On the other hand, at a relatively low temperature for diffusion into silicon, (e.g., 900° C.), a long diffusion time is required that gives a concentration doping gradient that extends relatively deep into the silicon. At the same time other doped areas in the device will diffuse out from their respective initial doping areas.
Consequently, very shallow doping requires a short time duration high temperature pulse. Ideally, the pulse would be a spike that rapidly rises to, and falls from, a high temperature. Similarly, for annealing, crystal damage resulting from a shallow implantation of doping material, a short high temperature pulse is required to maintain a sharply defined, shallow conductive area having a steep concentration gradient at the conductive area boundary. To obtain a short high temperature pulse in the wafer, a means is needed for a well controlled, very rapid, high heat input to the wafer.
High electrical conductivity structures in silicon semiconductor devices are in a non-equilibrium concentration regime. The concentration of doping atoms in the silicon structure is greater than the solubility of the doping material at ambient, operating temperature. Diffusing-or annealing the doping atoms at a high temperature and then cooling the silicon rapidly enough to “freeze” the impurity doping atoms into a single crystal structure, achieves this. In this way the doping concentration is set by the solubility of the doping atoms in silicon at the peak process temperature. A higher concentration of doping atoms in a single crystal structure gives a higher electrical conductivity.
Current Methods Under Investigation for Shallow Junction and Channel Formation
Ion implantation and anneal:
A high current, low energy ion implanter implants doping atoms to the required depth and concentration followed by a rapid thermal anneal of the damage. Two rapid anneal methods now used are radiant Rapid Thermal Processing (RTP) and fast furnace anneal RTP. Radiant RTP systems are reported to obtain a temperature rise rate of up to 300° C./sec, but significantly slower cool time, see the following paragraph and also FIG.
6
. Issues with this approach for future device generations requiring shallow implants and diffusion are:
Ion implanters have high capital cost
Limitations to current production Radiant RTP, see following paragraph
Radiant RTP:
Heat lamps rapidly heat the silicon wafer. Cooling is by contact with a cooled wafer holding plate. Radiant energy output from the lamps is largely in the Infra-Red (IR) range so that heating results from coupling mechanisms for IR energy to silicon. The primary coupling mechanism for heating silicon wafers is to free electrons that occur at temperatures above 700° C. issues with Radiant RTP for future generations of semiconductor devices are
Limited temperature rise and cooling. Currently most rapid temperature rise rates that are reported are of the order of 300° C./sec and cooling rates of the order of 90° C./sec.
Coupling of radiant energy into the wafer is dependent on the emissivity (related to the reflectivity) of the surface and is thus dependent on the pattern and material. For fast temperature rise and cooling local pattern dependent differences do not average out and non-uniform thermal processing results.
Heating mechanism occurs only for a wafer temperature greater than 700° C. Low temperature anneals, such as fast spike-like heating and cooling from 100° C. to 800° C., cannot be done.
Plasma immersion and anneal:
Instead of the scan implantation method used by ion implanters, the wafer is placed in a plasma that contains the doping material. A voltage pulse is applied to the wafer with respect to the plasma potential that drives doping ions into the wafer. A rapid thermal anneal removes the crystal damage from the plasma implant. The advantage of this approach is that it could provide ion implantation at a lower cost. Issues with this approach are the same as those set forth above for the ion implant technique as well as those above for the RTP anneal. In addition, problems include:
Obtaining full wafer doping uniformity
Controlling unwanted impurities driven into the wafer from the plasma
Projection Gas Immersion on Laser Doping (PGILD):
A laser scans the wafer in a process chamber with the doping gas. The intense, localized laser heating rapidly diffuses the doping material into the silicon. An advantage of this approach is that very high heating power can be “dumped” into the surface to provide extremely rapid heating and cooling. A fundamental issue with this approach is that coupling of the laser energy into the silicon is pattern and material dependent making repeatable uniform processing difficult. Laser annealing of implanted silicon is under investigation to take advantage of the very rapid temperature rise and cool times possible. However, the fundamental issue of the silicon heating being pattern and material dependent remains.
Rapid thermal gas doping:
The wafer is placed in a furnace containing the doping material as a gas. A rapid t
Bollinger Lynn David
Tokmouline Iskander
Jetek, Inc.
St. Onge Steward Johnston & Reens LLC
Wilczewski M.
LandOfFree
Method for rapid thermal processing of substrates does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for rapid thermal processing of substrates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for rapid thermal processing of substrates will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3226197