Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-03
2003-01-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06510548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to programmable logic devices and specifically to providing pre-designed modules for programmable logic devices.
2. Discussion of the Related Art
Programmable logic devices (PLDs) are well known in the art of integrated circuits. A PLD can be user-programmed in the field to implement logic designs. One type of PLD is the field programmable gate array (FPGA). In a typical architecture, an FPGA includes an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs). The IOBs provide the interface between the package pins and the CLBs, whereas the CLBs provide the functional elements for constructing logic on the FPGA. The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream into the FPGA. This configuration bitstream is generated using software tools.
Some FPGAs, like the Virtex FGPA, can be programmed to incorporate a block with a pre-designed functionality called a “core”. In one embodiment, a core can be a predetermined set of configuration bits that program the FPGA to perform one or more functions. In another embodiment, a core can include source code or schematics, which describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, memories, storage elements, and math functions. Cores can be provided with an optimally floorplanned layout for specific FPGAS. Cores can also be parameterizable, thereby allowing the user to enter parameters to activate or change certain core functionality.
FIG. 1
illustrates one design flow
100
for using one or more cores in an FPGA. In design flow
100
, a core generator
104
, activated by system level tools
101
, can receive one or more plug-in cores
102
provided by third parties. Alternatively, core generator
104
can use a core provided within a set of libraries
103
, wherein these libraries
103
form part of core generator
104
.
Once the core is selected, it can be provided to an FPGA software tool
106
. Such FPGA software could include the Alliance™, Foundation™, or Foundation ISE™ software, all licensed by the assignee of the present invention. This software also can receive a top-level design
105
provided by a user. This top-level design designates the logic design that, in addition to the core(s), will be implemented on the FPGA. In one embodiment, FPGA software tool
106
can receive top-level designs
105
in VHDL, Verilog, or in standard schematic form. FPGA software tool
106
generates the configuration bitstream that will program an FPGA
107
to provide the functions designated by the core(s) and top-level design.
As technology improvements are realized, more complex functionality, such as microprocessor and digital signal processing (DSP) functions, can be provided in cores. However, vencors currently providing this functionality in integrated circuits have concerns regarding converting this “hard” implementation to an FPGA implementation. Specifically, an FPGA implementation (i.e. a bitstream to implement the specific functionality) can be easily proliferated and subsequently used in other FPGAs without knowledge of the vendor. Thus, vendors offering FPGA IP (i.e. intellectual property associated with a logic design) currently have substantially less control over their IP than providing the same functionality in “hard” form. Therefore, a need arises for a method of providing a core while maintaining protection and control over its associated IP.
SUMMARY OF THE INVENTION
In accordance with the present invention, a vendor can designate the size and ports of a core, i.e. a pre-designed module, for a programmable logic device. The ports include at least one input port and at least one output port. Using this information, the user can generate a top-level design that can accommodate the core. The user can then submit that top-level design to the vendor, or a third party designated by the vendor, to generate a complete configuration bitstream for the PLD. The user can use this configuration bitstream to program the PLD, thereby implementing the top-level design including the core.
In one embodiment, the top-level design includes a placeholder for the core. The placeholder has a predetermined size, i.e. the size of the core, and includes the input and output ports designated for the core. A port can be defined by the signal it is designed to receive/output. The port can also be defined by the wire that carries that signal to/from the port. The user can use a model for simulating the functioning of the core, thereby allowing the user to test the complete top-level design.
In accordance with one embodiment of the present invention, a vendor can use standard tools to generate a configuration bitstream for a user. This configuration bitstream, in addition to including the bits for implementing the core provided by the vendor, also includes the bits for implementing the remainder of the user's logic design on the PLD. The number of bits in this configuration bitstream is typically large enough to render reverse engineering economically unfeasible. In this manner, the present invention allows vendors to retain control over their proprietary core IP and discourages undetectable use of this IP.
A third party designated by the vendor(s) of one or more cores could perform the merge of the user's design and the core(s), i.e. generate the configuration bitstream for the PLD. In one business model, this third party could have a license or a franchise for the core(s).
REFERENCES:
patent: 5946478 (1999-08-01), Lawman
patent: 6205574 (2001-03-01), Dellinger et al.
patent: 6301695 (2001-10-01), Burnham et al.
patent: 6305005 (2001-10-01), Burnham et al.
patent: 6324676 (2001-11-01), Burnham et al.
Bever Hoffman & Harms
Harms Jeanette S.
Kubodera John
Lin Sun James
Siek Vuthe
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