Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-06
2003-08-05
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S639000, C438S692000
Reexamination Certificate
active
06602780
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor manufacturing methods and more particularly to an improved method for manufacturing metalization vias and metal interconnects using low-k insulating inter-metal dielectric (IMD)layers.
BACKGROUND OF THE INVENTION
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been parasitic effects such as contact resistance in metal interconnects needed to interconnect lines between devices. As a way to overcome such a limitations, methods have been implemented to alleviate damage or other factors caused by etching that may increase the contact resistance in metal interconnects.
In the fabrication of semiconductor devices multiple layers may be required for providing a multi-layered interconnect structure. During the manufacture of integrated circuits it is common to place material photoresist on top of a semiconductor wafer in desired patterns and to etch away or otherwise remove surrounding material not covered by the resist pattern in order to produce metal interconnect lines or other desired features. During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer. Such holes are commonly referred to as contact holes, i.e., when the hole extends through an insulating layer to an active device area, or vias, i.e., when the hole extends through an insulating layer between two conductive layers.
Originally, conventional process techniques implemented multilevel interconnection systems by depositing a metal layer, photo-lithographically patterning the deposited metal layer, and then etching the metal layer to form desired interconnections. However, since metals are typically more difficult to pattern and etch than other semiconductor layers such as dielectric or oxide layers, manufacturing processes such as, for example, damascene processes, have been implemented to form metal vias and interconnects by dispensing entirely with the metal etching process. The damascene process is a well known semiconductor fabrication method for forming multiple layers of metalization vias and interconnect lines.
For example, in the dual damascene process, a via is etched in an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a metal or conductive layer. After a series of photolithographic steps defining via openings and trench openings, the via and the trench openings are filled with a metal (e.g., Al, Cu) to form metalization vias and interconnect lines, respectively. The excess metal above the trench level is then removed by well known chemical-mechanical polishing (CMP) processes.
One problem with the dual damascene process, especially where metal interconnect lines are adjacent to one another thereby making the distance between metal interconnect lines critical as design rules are scaled down, has been the phenomenon of coherent interference effects forming standing waves in the photoresist due to a reflecting underlayer, e.g., the insulating IMD/ILD layer. Light reflecting from an underlying substrate can lead to size variations in the photoresist pattern making it difficult for critical dimension (CD) control. In addition to size variations in the photoresist pattern, reflecting light may lead to undercutting the photoresist during a photoresist patterning process where portions of a photoresist layer that have been unintentionally exposed by scattered or reflected light near the reflecting interface are removed after photoresist development. Undercutting the photoresist layer acts to decrease the spacing between metallic lines, compromising device design and performance. Efforts to address this problem have included adding anti-reflectance coating (ARC) layers over the insulating layer prior to laying down a photoresist layer, thereby reducing unwanted light reflections.
In a typical damascene process, for example, a dual damascene manufacturing process known in the art as a via-first-trench last process, conventional photolithographic processes using a photoresist layer is first used to expose and pattern an etching mask on the surface of an etching stop layer overlying the insulating (IMD/ILD) layer, for etching via openings through the insulating layer. Subsequently a similar process is used to define trench openings that are formed substantially over the via openings which in turn define metallic interconnect lines. The via openings and trench openings are subsequently filled with metal to form metalization vias and metal interconnect lines. The surface may then be planarized by conventional techniques to better define the metal interconnect lines and prepare the substrate for further processing.
As an example of a typical damascene process, for example, a via-first process, a substrate having a first metallic layer is provided. Next, an insulating layer is formed over the substrate, followed by planarization so that the insulating layer thickness matches the depth of the desired via openings. Thereafter, an ARC layer followed by an etching stop layer is formed over the insulating layer. Next, a photoresist layer is formed over the etching stop layer, which is subsequently patterned as an etching mask. The patterned etching stop layer and insulating layer are then anisotropically etched to form via openings through the etching stop layer and insulating layer, where the resulting via openings are in communication with an underlying conductive layer.
After the via holes are etched, but before the holes are filled with a conductive material, the photoresist mask which remains on top of the desired features may be removed by a dry etching method known as a reactive ion etch (RIE) or ashing process in a quartz chamber using a plasma of O
2
or a combination of CF
4
and O
2
to react with the photoresist material.
However, another related problem during via hole etching arises due to the use of low-k (dielectric constant) insulating (IMD/ILD) layers. As semiconductor structure sizes have decreased, the necessity for the use of lower dielectric constant insulating layers has increased since lower dielectric constant materials lessen parasitic effects which can increase signal delay time constants.
In many cases, materials that have physical properties that are otherwise acceptable for use as low-k materials in, for example, an insulting layer, also have the undesirable property of being hygroscopic or have a high affinity for moisture. Thus, during the RIE etching step in an oxygen containing plasma to remove the photoresist used to pattern the via openings or trench openings, the low-k material produces hydrophilic bonds and absorbs moisture. During subsequent metal deposition to fill the via holes and trench openings to form metal interconnects, outgassing of the moisture occurs, causing oxidation of metal contacts resulting in via poisoning, or high resistivity of the via interconnect due to the oxidized metal contacts or interconnects.
To overcome this problem, methods have been developed that, for example, provide a protective etch stop liner deposited conformally over the inside of the via opening after via etching to protect the low-k insulating layer. For example, referring to
FIG. 1
, is shown a via opening
10
after via etching but prior to depositing an etch liner. The via opening
10
extends from a surface
12
through an etch stop layer
14
(e.g., SiON), and ARC layer
16
(e.g., SiON) and at least partially through an insulating layer
18
.
FIG. 2
shows the conformally deposited SiON etch liner
20
. The SiON etch liner
20
overlies the SiON ARC layer
16
and etch stop layer
14
and is deposited prior to applying photoresist layer
22
for patterning of the trench openings
24
to form metal inter
Bao Tien-I
Ko Chung Chi
Li Lih Ping
Lu Yung-Cheng
Shih Tsu
Pham Long
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
Weiss Howard
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