Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-20
2004-02-10
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S586000, C438S233000, C438S303000
Reexamination Certificate
active
06689655
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a process for the use of a local interconnection architecture of a memory cell and more particularly to improve the density at the scale of an elementary cell of an integrated circuit, for example a DRAM or SRAM type memory cell.
2. Description of Related Art
In this type of cell, the local interconnection level (LIL) is made before the first metal deposit.
FIG. 1
illustrates the context of the invention. The local interconnection level
1
is composed of a pad preferably made from tungsten, the function of which is to connect the access transistor
2
of the cell that is formed on the substrate made of silicon Si at the top contact
3
.
In order to make the tungsten interconnection level, a series of special steps is applied immediately after formation of the polysilicon grid
2
g
and the nitride type spacers
2
e
and
2
e
′ located on each side of the transistor grid
2
g
. These steps consist of making an oxide OX deposit and making the etching that defines the recess of the interconnection pad in the oxide layer using a mask. Conventionally, the step in which the layer oxide OX is deposited is preceded by a step in which a nitride film is deposited to protect the isolation trenches
4
if the oxide layer is etched to make the local interconnection level straddle over isolation trenches.
The Shallow Trench Isolations (STI) that are intended to isolate cells from each other to avoid the parasitic electrical effects of a transistor on its neighbor are filled with oxide.
Thus, etching at the local interconnection level is done in two steps. First, the oxide layer is etched, the nitride film then acts as a stop layer due to the known selectivity between the oxide and nitride materials, and second the nitride film is then etched in turn.
In the particular interconnection architectures shown in
FIG. 2
, the LIL
1
is straddled over the grid
2
g
of transistor
2
in order to save density and therefore reduce the size of each cell.
This technique although useful, is not without its problems. One problem that then arises is to isolate the polysilicon forming the tungsten transistor grid forming the interconnection pad, in order to avoid short circuits.
Several architectures of this type are already known in prior art. However, none is fully satisfactory.
One solution according to prior art to make the local interconnection level straddle over the transistor grid while avoiding electrical contact between the polysilicon of the grid and the tungsten of the interconnection pad consists of making the transistor grid using a hard dielectric mask for example from nitride, that will remain on the polysilicon of the grid.
This is why, as shown in
FIG. 3
, the polysilicon in grid
2
g
of the transistor will be covered by a double layer composed of the hard nitride mask
5
and the nitride film
6
that is deposited before the specific steps prior to production of the LIL to protect the isolation trenches
4
.
Thus, due to this double protection, a residual nitride thickness will remain above the polysilicon forming the transistor grid after etching the local interconnection pad produced in two phases a and b through the mask M.
The two phases a and b are applied to etch the oxide layer OX and the nitride film
6
as described above, respectively.
The interconnection pad can then straddle over the transistor grid
2
g
without the need for any electrical contact between the polysilicon of the grid and the tungsten forming the interconnection pad. The dielectric covering the grid then isolates the polysilicon and prevents any electrical link with the local interconnection level.
However, this solution according to prior art has a major disadvantage. One disadvantage, using this prior art process for producing the transistor grid, is that it cannot be used to form a silicide on the transistor grid.
This type of treatment of the transistor grid and its other active parts that consists of depositing a cobalt layer and increasing the temperature in order to initiate a selective reaction forming a deposit of cobalt silicon CoSi
2
at the recesses of the silicon and polysilicon, has become unavoidable. This silicidation treatment reduces the input resistance of the transistor by several orders of magnitude.
The transistor grid in the solution according to prior art was made with a hard nitride dielectric mask that remains on the polysilicon, consequently the silicidation reaction between the cobalt and the polysilicon can no longer be carried out.
Therefore, with this solution it is impossible to increase the density while straddling the local interconnection level over the transistor grid, and also benefit from the grid silicidation treatment.
A choice has to be made which limits the attractiveness of this solution.
Another solution according to prior art to prevent any electrical contact between the polysilicon and the tungsten when the local interconnection level LIL straddles over the transistor grid is presented with reference to
FIGS. 4A and 4B
.
The construction with reference to
FIG. 4A
requires an oxide layer OX to be deposited on transistor
2
, and then a second mask M should be added that is complementary to the grid lines, in other words the mask that was used for formation of the grid
2
g
of transistor
2
.
Thus, mask M can open the oxide layer OX only above the grid
2
g
of transistor
2
by using a particular chemical attack.
As shown in
FIG. 4
b
, a dielectric layer
5
acting as protection and insulation for the grid
2
g
of transistor
2
, for example a nitride layer, is then added into the opening previously created in the oxide layer and covering the entire polysilicon of the grid.
However, the disadvantage of this construction according to prior art is that it is essential that the opening of mask M is positioned precisely above the grid.
Therefore, the alignment of the mask over the grid must be perfect. The consequence of the slightest offset in the recess of the mask will be that the polysilicon in the grid will not be fully covered by the dielectric protection.
However in existing technologies, grid sizes tend towards orders of magnitude of the order of 100 nanometers, while alignment tolerances for making cells are not better than the order of 45 nanometers.
Thus, due to these tolerance problems in producing the photo for a mask, this solution is unsuitable for technologies that use increasingly small components.
Accordingly, a need exists to over come these disadvantages of the prior art and to provide a process to a protection to the polysilicon forming the grid of a transistor and to electrically isolate the local interconnection pad in architectures in which the interconnection pad straddles over the transistor grid.
Moreover, a need exists to over come these disadvantages of the prior art and to provide a process to ensure that the protection used for the polysilicon in the grid so it remains compatible with the silicidation treatment of active areas of the transistor and the grid made in advance.
SUMMARY OF THE INVENTION
The present invention uses a dielectric-conducting pair on the grid, and therefore to make a double layer in which a polysilicon layer is introduced to use the selectivity principle, which is large considering etching of the polysilicon with respect to the oxide in which the LIL interconnection pad is formed.
Therefore, the invention relates to a process for the protection of the grid of a transistor in an integrated circuit to make an local interconnection pad straddling over the grid and the silicon substrate on which it is formed, characterized in that it comprises:
deposit a nitride layer and then a polysilicon layer on the silicon substrate and on the grid to form a double dielectric-conducting layer;
deposit an oxide layer to cover the double dielectric-conducting layer;
remove the oxide layer under the grid level to expose the top part of the double layer above the grid;
use a mask for an etching step to remove the polysilic
Coronel Philippe
Ferreira Paul
Leverd Francois
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Gibbons Jon A.
Huynh Yennhu B
Jorgenson Lisa K.
STMicroelectronics S.A.
LandOfFree
Method for production process for the local interconnection... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for production process for the local interconnection..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for production process for the local interconnection... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3342678