Method for production of charge-trapping memory devices

Details Method for production of charge-trapping memory devices Method for production of charge-trapping memory devices

2006-04-11

2006-04-11

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S288000, C438S591000, C438S954000

Reexamination Certificate

active

07026220

ABSTRACT:
The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.

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