Method for production of a memory cell arrangement

Details Method for production of a memory cell arrangement Method for production of a memory cell arrangement

2001-01-31

2002-11-05

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S276000, C438S278000, C257S331000, C257S392000

Reexamination Certificate

active

06475866

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for producing a memory cell arrangement, and particularly to a memory cell having vertical transistors.
2. Description of the Related Art
In order to store large volumes of data, for example for DP (data processing) applications or for the digital storage of music or images, use is mainly made at present of memory systems which have mechanically movable parts such as, for example, hard disk memories, floppy disks or compact discs. The moved parts are subject to mechanical wear. Furthermore, they require a comparatively large volume and permit only slow data access. Moreover, since they are sensitive to vibrations and position and have a comparatively high power consumption for their operation, these memory systems can be used is mobile systems only to a limited extent.
In order to store relatively small volumes of data, semiconductor-based read-only memories are known. These are often realised as a planar integrated silicon circuit is which MOS transistors are used as memory cells. The transistors are selected via the gate electrode, which is connected to the word lice. The input of the MOS transistor is connected to a reference line and the output is connected to a bit line. During the read operation, it is assessed whether or not a current is flowing through the transistor. The logic values zero and one are assigned correspondingly. The storage of zero and one is effected in technical terms is that no MOS transistor is produced or no conductive connection to the bit lice is realised in memory cells is which the logic value assigned to the state “no current flow through the transistor” is stored. As an alternative, MOS transistors which have different threshold voltages due to different dopant concentrations is the channel region can be realised for the two logic values.
These semiconductor-based memories permit random access to the stored information. The electrical power required to read the informatics is distinctly less than is the case of the abovementioned memory systems having mechanically movable parts. Since no movable parts are required, mechanical wear and sensitivity to vibrations are no longer a problem here either. Semiconductor-based memories can therefore be used for mobile systems as well.
The silicon memories described generally have a planar structure. A minimum area requirement thus becomes necessary for each memory cell and is 4 F
2
in the most favourable case, F being the smallest structure size that can be produced with the respective technology.
A read-only memory cell arrangement whose memory cells comprise MOS transistors is disclosed in German Patent document DE 42 14 923 A1. These MOS transistors are arranged along trenches in such a way that a source region adjoins the bottom of the trench, a drain region adjoins the surface of the substrate and a channel region adjoins the side and bottom of the trench both vertically with respect to the surface of the substrate and parallel to the surface of the substrate. The surface of the channel region is provided with a gate dielectric. The gate electrode is designed as a side covering (spacer). The logic values zero and one are differentiated by different threshold voltages, which are effected by channel implantation. During the channel implantation, the implanting ions impinge on the surface of the respective trench at as angle such that implantation is deliberately effected only along one side due to shading effects of the opposite side. In this memory cell arrangement, the word lines run as spacers, along, the sides of the trenches.
Japanese Patent document JP-A 4-226071 discloses a further memory cell arrangement, which comprises vertical MOS transistors arranged on the sides of trenches as memory cells. In this case, diffusion regions which in each case form the source/drain regions of the vertical MOS transistors run on the bottom of trenches and between adjacent trenches. The word lines, which comprise the gate electrodes of the vertical MOS transistors, run perpendicularly to the trenches. The threshold voltage of the vertical MOS transistors is sat by means of angled implantation.
U.S. Pat. No. 4,663,644 discloses a memory cell arrangement whose memory cells comprise vertical MOS transistors. These vertical MOS transistors are each arranged on the aides of trenches. The word lines, which each comprise the gate electrodes of the vertical MOS transistors, are arranged is the trenches. Two word lines are arranged is each trench. The bit lines are realised as conductor tracks on the surface of the substrate. The contact between the bit lines and the respective source/drain regions which adjoin the surface of the substrate is realised via a contact hole. The source/drain regions which adjoin the bottom of the trenches are realised as a continuous doped layer and are put at the reference potential. In this memory cell arrangement, the information is stored is the form of threshold voltages, having different levels, of the MOS transistors. The different threshold voltages are realised by different dopant concentrations in the channel region of the MOS transistors. In order to form as increased dopant concentration is the channel region, a doped layer is deposited and is structured in such a way that sides in which increased dopant concentrations are to be formed remain covered by the structured dopant layer. The channel regions having as increased dopant concentration are formed by outdiffusion of the structured dopant layer.
In order to increase the effective storage density, it has furthermore been proposed (see, for example, the publication by Yasushi Kubota, Shinji Toyoyama, Yoji Kanic, Shuhei Tsuchimoto “Proposal of New Multiple-Valued Mask-ROM Design” IEICE Trans. Electron Vol. E77, p. 601, April 1994), to program a semiconductor memory arrangement having planar MOS transistors in the sense of multi-value logic. This procedure is also referred to as multi-level programming. In this case, the MOS transistors are produced in such a way that they have four different threshold voltage values depending on the stored information. Each of the threshold voltage values is then assigned two logic values, that is to say “0” and “0”, “0” and “1”, “1” and “0” or “1” and “1”. In this way, the effective storage density rises by a factor of two since two logic values are stored is each memory call without the area of the memory cell changing as a result of this. The different threshold voltage values are realised by different channel dopings. Masked implantation is carried out for each threshold voltage value. Four additional masks are therefore necessary for multi-level programming.
SUMMARY OF THE INVENTION
The problem underlying the invention is that of specifying a semiconductor-based memory cell arrangement in which as increased storage density is achieved and which can be produced with few production steps and a high yield. Furthermore, it is intended to specify a method for the production of such a memory cell arrangement.
The present invention solves the foregoing problems by a method for the production of a memory cell arrangement, in which strip-like trenches which essentially run in parallel are formed in a main area of a substrate which comprises, at least in the region of the main area, semiconductor material which is doped by a first conductivity type, in which MOS transistors which are vertical with respect to the main area are formed on the sides of the trenches, act as memory cells and have at least three different threshold voltage values depending on the stored information, in which a first threshold voltage value is realized by the thickness of the gate dielectric and a second and a third threshold voltage value are realized by different channel dopings.
In a preferred method, strip-like, doped regions, which are doped by a second conductivity type opposite to the first, are formed on the bottom of the trenches and on the main area between adjacent trenches, in which an insulating layer is

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