Method for producing two gates controlling the same channel

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S267000, C438S303000, C438S596000, C257SE21421

Reexamination Certificate

active

11339101

ABSTRACT:
A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate channel (71) subsequently defined in the substrate (11) by source/drain regions (82, 102, 84, 104) that are implanted around the etched gate structures (72, 74). Depending on how the first spacer structure (42) is positioned and configured, the channel (71) may be controlled to provide either a logical AND gate (100) or logical OR gate (200) functionality.

REFERENCES:
patent: 6124174 (2000-09-01), Gardner et al.
patent: 7064022 (2006-06-01), Hill et al.
patent: 2005/0064661 (2005-03-01), Lee et al.
S. Bhattacharya et al., “Improved Performance and Reliability of Split Gate Source-Side Injected Flash Memory Cells,” 1996, IEEE, pp. 339-342.
K. Takahashi et al., “A0.9V Operation 2-Transistor Flash Memory for Embedded Logic LSIs,” 1999 Symposium on VLSI Technology Digest of Technical Papers, pp. 21-22.
M. Orlowski et al., U.S. Appl. No. 11/240,242, filed Sep. 30, 2005, entitled “A Method of Making a Multi-Bit Non-Volatile Memory (NVM) Cell and Structure”.

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