Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1997-09-15
1999-09-21
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438149, 438154, 438162, 438219, 438407, 438404, H01L 2176
Patent
active
059565977
ABSTRACT:
According to a preferred embodiment of the present invention, a stress-reducing region formed on a wafer allows standard bulk CMOS (non-SOI) devices and SOI devices to be reliably fabricated on the same wafer. The high-stress interface that typically exists between the SOI device regions and the non-SOI device regions is transferred to a region where the high-stress will be reduced and relaxed. Typically, this means that the high-stress interface will be fabricated so as to lie over a region of the wafer similar to Shallow Trench Isolation (STI) regions. In addition, by using another preferred embodiment of the present invention, a coplanar wafer surface can be maintained for a wafer which includes both bulk CMOS devices and SOI devices. This is accomplished by etching the silicon wafer in the SOI device regions prior to the oxygen implantation so that the surface of the area between the stress interface regions is lower than the overall surface of the remainder of the wafer. Then, when the SiO.sub.2 region is formed for the SOI devices, the expansion of the SOI region will bring the surface of the SOI device area up to the overall surface of the wafer. A short Chemical Mechanical Polish (CMP) step may also be included to ensure uniformity of the wafer's surface.
REFERENCES:
patent: 5399507 (1995-03-01), Sun
patent: 5529947 (1996-06-01), Okonogi
patent: 5573972 (1996-11-01), Kobayashi
patent: 5726089 (1998-03-01), Okonogi
Furukawa Toshiharu
Hakey Mark C.
Holmes Steven J.
Horak David V.
Rabidoux Paul A.
Dang Trung
International Business Machines - Corporation
Shkurko Eugene I.
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