Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-10
2002-01-01
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S263000, C438S266000, C438S279000
Reexamination Certificate
active
06335244
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a nonvolatile semiconductor memory device, and a method for producing the same. More specifically, the invention relates to a nonvolatile semiconductor memory device having a stacked gate type transistor, and a method for producing the same.
2. Description of the Related Background Art
A typical nonvolatile semiconductor memory device is provided with a cell transistor forming region for forming a cell transistor for nonvolatilisably accumulating charges, a selecting transistor forming region for forming a selecting transistor for selectively operating the cell transistor, and a peripheral transistor forming region for forming a peripheral transistor for the cell transistor and the selecting transistor.
The cell transistor has a two-layer structure which comprises a first polysilicon layer constituting a floating gate, and a second polysilicon layer constituting a control gate. Therefore, in order to flatten the surface of a nonvolatile semiconductor memory device, it is desired that the peripheral transistor and the selecting transistor have a two-layer structure. That is, it is desired that the height of the cell transistor in the cell transistor forming region is the same as the height of the selecting transistor in the selecting transistor forming region. Moreover, it is desired that the height of the cell transistor in the cell transistor forming region is the same as the height of the selecting transistor in the peripheral transistor forming region.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a nonvolatile semiconductor memory device wherein the height of a cell transistor in a cell transistor forming region is the same as the height of a selecting transistor in a selecting transistor forming region.
It is another object of the present invention to provide a nonvolatile semiconductor memory device wherein the height of a cell transistor in a cell transistor forming region is the same as the height of a peripheral transistor in a peripheral transistor forming region.
It is a further object of the present invention to provide a nonvolatile semiconductor memory device wherein the surface of an interlayer insulator film is flattened when the interlayer insulator film is formed on a semiconductor transistor, a selecting transistor and a peripheral transistor.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, there is provided a method for producing a nonvolatile semiconductor memory device which has a cell transistor forming region, in which a cell transistor is formed, and a non-cell transistor forming region, in which at least one of a peripheral transistor and a selecting transistor is formed, the method comprising the steps of: forming a first insulator film on a semiconductor substrate; forming a first conductive film on the first insulator film; forming a second insulator film on the first conductive film; forming a second conductive film on the second insulator film; forming a mask film on the second conductive film; patterning the mask film to form a cell mask film in the cell transistor forming region, and a transistor mask film in the non-cell transistor forming region; etching the second conductive film using the cell mask film and the transistor mask film as masks to form a control gate in the cell transistor forming region, and a second gate electrode in the non-cell transistor forming region; etching the second insulator film using the cell mask film and the transistor mask film as masks to form an intergate insulator film in the cell transistor forming region and the non-cell transistor forming region; forming a resist pattern in the non-cell transistor forming region so that a part of the resist pattern overlaps with the transistor mask film; and etching the first conductive film using the cell mask film, the transistor mask film and the resist pattern as masks to form a floating gate in the cell transistor forming region, and a first gate electrode in the non-cell transistor forming region.
According to another aspect of the present invention, there is provided a method for producing a nonvolatile semiconductor memory device comprising: a cell transistor which is formed on a semiconductor substrate and which has a cell insulator film, a floating gate, a first intergate insulator film, a control gate and a cell mask film; and a transistor which is formed on the semiconductor substrate and which has a transistor insulator film, a first gate electrode, a second intergate insulator film, a second gate electrode and a transistor mask film, the method comprising the steps of: sequentially forming a first insulator film, a first conductive film, a second insulator film, a second conductive film and a mask film on a semiconductor substrate; patterning the mask film to form the cell mask film and the transistor mask film; etching the second conductive film and the second insulator film using the cell mask film and the transistor mask film as masks to form the control gate and the second gate electrode and to form the first intergate insulator film and the second intergate insulator film; forming a resist pattern so that a part of the resist pattern overlaps with the transistor mask film; and etching the first conductive film using the cell mask film, the transistor mask film and the resist pattern as masks to form the floating gate and the first gate electrode.
REFERENCES:
patent: 5326999 (1994-07-01), Kim et al.
patent: 5846861 (1998-12-01), Saitoh
patent: 6268247 (2001-07-01), Cremonesi et al.
Bowers Charles
Chen Jack
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