Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-08
2001-06-12
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S620000, C438S636000, C438S700000, C438S952000
Reexamination Certificate
active
06245656
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for producing multi-level contacts, and more particularly, relates to a method which incorporates an anti-reflective coating (ARC) as a hard mask in production of multi-level contacts.
2. Description of the Prior Art
As integration density of integrated circuits increases, critical dimensions of devices become smaller and more demands on photolithographic and etching processes arise It is a challenge to shrink critical dimensions of devices so as to cary out flirther shrinking dimensions of next generation devices.
Near ultraviolet light or deep ultraviolet light is applied to expose and define patterns in photolithographic process and puts much influences on pattern resolution. From g-line (436 nm) and i-line (365 nm) to KrF (248 nm), light sources with decreasing wave lengths help to improve resolution and help to shrink critical dimensions of line width. However, light sources with decreasing wave lengths have narrower depths of focus and will result in poor exposure. Furthermore, swing curves of light intensity or line width versus depths of a photoresist increase in amplitudes and standing wave effects are amplified.
In producing multi-level contacts having shrunk critical dimensions, problems of light interference become even serious. Reflective light from multiple levels varies with line width and thus uniformity is deteriorated. Standing wave effects and notching even worsen the process. Furthermore, steps of etching for contacts with multiple levels are difficult to control.
In conventional methods for producing multi-level contacts, the line width of contacts varies, depending on the depths of contacts, because reflective lights from the first reflective surface travel or different distances. Light interference is more complicated. Contacts in the same exposure area may receive different exposure light intensities because the depths of contacts differ. Additionally, the shrunk dimensions of the line width increase light interference. In steps of etching and forming contacts after exposure, etching end points are hard to control since every multi-level contact has a different etching depth.
The conventional method for producing multi-level contacts is described hereinafter with reference to
FIG. 1. A
masking photoresist
12
is patterned on a dielectric layer
13
which is superimposed on a silicon substrate
11
. In general, the dielectric layer
13
is made of a borophosphosilicate glass (BPSG), tetraethyl-orthosilicate (TEOS) or other dielectric materials. Devices which are defined respectively by an isolation layer
14
, tungsten silicide
15
and polysilicon
16
are formed on the substrate
11
. An incident light
17
is projected onto the dielectric layer
13
via an unmasked area and part of the light
17
arrives at the devices and then is reflected. The reflected light either exposes the photoresist
12
or interferes with the incident light
17
. Standing wave effects occur and poor profiles are thus made. In the step of etching after exposure, etching end points are hard to control. If the etching step stops at a deep position, photoresist loss may occur and devices at a high level may be excessively etched and damaged. However, if the etching step stops at a less deep position, devices at a low level may have residues thereon and may have high contact resistance.
U.S. Pat. No. 4,758,305 uses multi-level photoresist, over-exposure and over-development to produce a spacer wall in the formation of contacts which can be applied for 0.8 &mgr;m to 1.25 &mgr;m patterns. Not any hard mask is required. The contacts thus formed are with one single depth. The problems of multi-level contacts are not solved or even raised. U.S. Pat. No. 5,355,020 discloses semiconductor devices having multi-level metal contacts in which planarization and anti-reflection techniques are applied. The ‘multi-level’ in the multi-level metal contacts refers to a multiple layer of metal lines, and the planarization and anti-reflection techniques are applied in production of metal lines.
For difficulties of control in contact hole diameters, which are caused by the multi-level contacts having contact holes of various depths, conventional methods do not provide solutions.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for producing multi-level contacts, which mainly focuses on solving problems of reflective lights from multiple levels.
One object of the present invention is to provide a method for producing multi-level contacts for combining reflective lights from multiple levels of reflective into one single light and for reducing interference of the reflective lights.
Another object of the present invention is to provide a method for producing multi-level contacts for preventing multi-level contacts from being overetched and photoresist loss.
A further object of the present invention is to provide a method for producing multi-level contacts for controlling dimensions of multi-level contacts and for expanding process windows and for increasing production yields. The critical dimensions of contacts can be further shrunk towards advanced process of next generation.
To overcome problems with conventional methods and to achieve the above objects, the present invention discloses a method for producing multi-level contacts, comprising the steps of: (a) providing a dielectric layer on a substrate which has a plurality of devices formed at various levels above the substrate; (b) forming a reflective coating on the dielectric layer; (c) forming an anti-reflective coating on the reflective coating; and (d) etching the dielectric layer and forming a plurality of contacts, wherein the reflective coating and the anti-reflective coating serve as etching hard masks and bottoms of the plurality of contacts respectively reach the plurality of devices.
The present invention further discloses a method for producing semiconductor devices, comprising the steps of: (a) forming a plurality of devices on a substrate; (b) forming a reflective coating of titanium compound and an anti-reflective coating of silicon oxynitiide on the substrate; and (c) etching the reflective coating and the anti-reflective coating to form a plurality of multi-level contacts on the substrate, wherein the reflective coating and the anti-reflective coating serve as etching hard masks and bottoms of the plurality of contacts respectively reach the plurality of devices.
The present invention adopts a reflective coating and an anti-reflective coating which also serve as an etching hard mask. By the introduction of the reflective coating, the reflective lights from multiple levels are reduced to those from a single level. The reflective lights from various levels can be eliminated by the incident lights which have 180° phase shift. The reflective coating and the anti-reflective coating can also serve as an etching hard mask and prevent overetching and photoresist loss during etching.
Problems of light interference and overetching can be solved by the method of the present invention and an improved profile of contacts can be obtained.
REFERENCES:
patent: 4758305 (1988-07-01), Bonifield et al.
patent: 5355020 (1994-10-01), Lee et al.
patent: 5854124 (1998-12-01), Lin
patent: 6030541 (2000-02-01), Adkisson et al.
patent: 6080662 (2000-06-01), Chen et al.
patent: 6090674 (2000-07-01), Hsieh et al.
patent: 6103456 (2000-08-01), Tobben et al.
patent: 6114235 (2000-09-01), Foote et al.
patent: 6121098 (2000-09-01), Strobl
Chang Shih-Ming
Chen Bi-Ling
Jeng Erik S.
Gurley Lynne A.
Niebling John F.
Vanguard International Semiconductor Corporation
Wood Herron & Evans L.L.P.
LandOfFree
Method for producing multi-level contacts does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing multi-level contacts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing multi-level contacts will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2519097