Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-04-17
2007-04-17
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S235000
Reexamination Certificate
active
10450006
ABSTRACT:
The invention relates to a method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip. In order to produce these high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip, all technological method steps for producing the vertical structure of the collector, base and emitter in the active region of the npn bipolar transistors as well as for laterally structuring the collector regions, base regions and emitter regions are performed before the troughs and the gate insulating layer for the MOS transistors are produced.
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Heinemann Bernd
Knoll Dieter
Chaudhari Chandra
IHP GmbH-Innovations for High Performance Microelectronics/Insti
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