Method for producing field effect device that includes...

Details Method for producing field effect device that includes... Method for producing field effect device that includes...

2008-05-06

2008-05-06

Smoot, Stephen W (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S481000, C257SE21094

Reexamination Certificate

active

07368358

ABSTRACT:
A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body. The SiGe source/drain forms a heterojunction and a metallurgical junction with the Si body that coincide with each other with a tolerance of less than about 10 nm, and preferably less than about 5 nm. The heterostructure source/drain is instrumental in reducing short channel effects. These structures are especially advantageous for PMOS due to increased hole mobility in the compressively strained SiGe channel. Representative embodiments include CMOS structures on bulk and on SOI.

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Ouyang et al. “A Novel Si/SiGe Heterjunction pMOSFET—” IEEE Trans. Electron Devices vol. 47, No. 10, 2000, pp. 1943-1949.

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