Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-08-29
1998-06-23
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438548, 438563, 438564, 438168, 438216, 438312, 438324, H01L 218238
Patent
active
057704902
ABSTRACT:
A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.
REFERENCES:
patent: 4755478 (1988-07-01), Abernathe et al.
patent: 5190888 (1993-03-01), Schwalke et al.
patent: 5329138 (1994-07-01), Mitani et al.
patent: 5464789 (1995-11-01), Saito
patent: 5465000 (1995-11-01), Williams
IBM Technical Disclosure Bulletin.backslash.vol. 31 No. 7.backslash.Dec. 1988.backslash.Dual Work Function Doping.
IBM Technical Disclosure Bulletin.backslash.Vo.26 No. 10A.backslash.Mar. 1984.backslash.Oxidizable P-Channel Gate Electrode.
Dialog 1996 Derwent Info. Ltd..backslash.Mar. 1996.backslash.p. 2.backslash.JP 6283725.
BU889-0198.backslash.Low Reistivity Stack for Dual Doped Polysilicon Gate Electrode.backslash.Jun. 1991. No. 326.backslash.Kenneth Mason Publications Ltd., England.
Frenette Robert O.
Hallock Dale P.
Mongeon Stephen A.
Speranza Anthony C.
Tonti William R. P.
International Business Machines - Corporation
Niebling John
Pham Long
Walter, Jr. Howard J.
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