Method for producing charge-trapping memory cell arrays

Details Method for producing charge-trapping memory cell arrays Method for producing charge-trapping memory cell arrays

2005-06-29

2008-09-23

Graybill, David E (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

07427548

ABSTRACT:
A memory layer sequence comprising a lower confinement layer (2), a charge-trapping layer (3), and an upper confinement layer (4) is applied on the main surface of a silicon substrate (1). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active area. A trench filling (7) is applied by growth or deposition of dielectric material or by a selective oxidation of the substrate material. After the removal of the charge-trapping layer sequence in a peripheral area and the deposition of a gate dielectric material provided for the transistors of an addressing circuitry, wordline stacks (8) are formed.

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patent: 6972226 (2005-12-01), Deppe et al.
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patent: WO 2005/096382 (2005-10-01), None
Eitan, B., et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.

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