Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
1999-03-30
2001-01-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S239000, C438S240000, C438S396000
Utility Patent
active
06168988
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for producing an integrated semiconductor memory configuration.
Semiconductor-based memory configurations usually include a number of memory cells each having a selection transistor and a storage capacitor connected to the selection transistor. A method for producing such memory configurations usually includes applying first electrodes over conductive connections. In each case, one of the conductive connections connects one of the first electrodes to one of the selection transistors. A storage dielectric is applied over the first electrode and, in turn, a second electrode is applied on the storage dielectric. As a result, the first and second electrodes as well as the intermediate storage dielectric form a storage capacitor which is connected to one of the selection transistors.
A memory configuration of that type is disclosed, for example, in Japanese Patent Publication No. 5-343615(A). The known semiconductor memory configuration has a first and a second electrode which are disposed on the surface of an insulation layer above the semiconductor body and are perpendicular to the surface of the insulation layer.
One use of novel ferroelectric materials as a storage dielectric of storage capacitors enables semiconductor memories to be produced which do not lose their information that is stored in the form of an electric charge after a failure of a supply voltage and/or which have memory contents that do not have to be refreshed at regular intervals due to leakage currents that occur.
What is critical in the course of using most of the previously known ferroelectric materials of that type is their processing within a semiconductor process. Most of the ferroelectric materials of that type are deposited at high temperatures in an oxygen-containing atmosphere. The use of ferroelectric materials of that type in the method described above, in which the storage dielectric is applied over the first electrode that, in turn, is situated over a conductive connection to one of the selection transistors, results in oxidation of the conductive connection. That is because during the deposition of the ferroelectric materials, oxygen diffuses through the first electrode in the direction of the conductive connection and oxidizes the latter. Oxidation of the conductive connection means an interruption of the electrical connection between the storage capacitor and the selection transistor of a memory cell, with the result that the latter is no longer functional.
Solution approaches for the purpose of avoiding oxidation of the conductive connection during the deposition of a ferroelectric storage dielectric provide for the application of barrier layers between the conductive connection and the first electrode. In that case the barrier layers must be electrically conductive but resistant to oxidation and the diffusion through of oxygen. What is disadvantageous about using barrier layers is the difficult search for suitable materials which are both electrically conductive and oxygen-impermeable, resistant to oxidation and can be applied in a suitable manner to the conductive connections.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for producing integrated barrier-free semiconductor memory configurations, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type, in which ferroelectric materials can be used to produce storage dielectrics of storage capacitors to be produced and in which the use of barrier layers between a conductive connection and a first electrode can be dispensed with, with the result that, in particular, the disadvantages mentioned above do not arise.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing an integrated semiconductor memory configuration, which comprises providing a configuration of selection transistors in a semiconductor body and an insulation layer disposed above the semiconductor body, the selection transistors having source regions; producing contact holes in the insulation layer above the source regions within the semiconductor body; applying an auxiliary layer on a surface (first main area) of the insulation layer and subsequently forming cutouts in the auxiliary layer defining side areas of the cutouts; producing first electrodes on the side areas of the cutouts; applying a storage dielectric to the first electrodes defining free areas of the storage dielectric; applying a second electrode to the free areas of the storage dielectric; removing the auxiliary layer; and producing conductive connections each connecting a respective one of the first electrodes and the source region of a respective one of the selection transistors.
In the inventive method for producing a memory configuration, the production of a conductive connection between one of the two electrodes, in this case the first electrode, and the selection transistor, is effected only after the storage dielectric has been deposited.
The method is suitable for the use of any desired dielectrics as storage dielectrics of storage capacitors in integrated semiconductor memory configurations. It is particularly suitable for the use of ferroelectric materials as storage dielectrics, since in this method the above-mentioned problems such as the oxidation of the conductive connection to the selection transistors during the deposition of the storage dielectric cannot occur. Furthermore, the method can easily be implemented with previously known methods for producing memory configurations.
In accordance with another mode of the invention, various methods are conceivable for the production of the first electrodes on the side areas of the cutouts. One embodiment of the invention provides for the first electrodes to be produced by the deposition of a first layer made of electrode material in the direction of the first main area. The first layer is subsequently subdivided into portions of the area of the later first electrode. The subdivision is preferably effected by removal of the first layer from areas of the auxiliary layer which run parallel to the first main area and/or from uncovered regions of the first main area. Uncovered regions of the first main area may arise, for example, as a result of the production of cutouts in the auxiliary layer. The auxiliary layer is completely removed in the region of the cutouts. The cutouts preferably have a rectangular cross section, with the result that the first electrodes which are produced are disposed approximately perpendicularly on the first main area.
In accordance with a further mode of the invention, the application of the storage dielectric to the first electrodes and the subsequent application of the second electrodes are preferably effected by successive deposition of a dielectric layer and of a second layer made of electrode material in the direction of the first main area. The two layers are subsequently removed preferably from the areas of the auxiliary layer which run parallel to the first main area and are situated outside the cutouts. It is necessary to remove the two layers from the areas of the auxiliary layer which run parallel to the first main area in order to be able to remove the auxiliary layer in the next method step.
In accordance with an added mode of the invention, in order to stabilize the storage capacitors, which include the first electrode, the storage dielectric and the second electrode and stand approximately perpendicularly on the first main area in the event of the use of cutouts having a rectangular cross section, after the removal of the auxiliary layer, a stabilization layer is deposited in the direction of the first main area, and the stabilization layer is subsequently partially removed, together with the dielectric layer and the second layer, from areas of the auxiliary layer which run parallel to the first main area. Residues of the stabilization layer remain behind in the cutouts aft
Hartner Walter
Hintermaier Frank
Mazure-Espejo Carlos
Schindler G{umlaut over (u)}nther
Greenberg Laurence A.
Infineon - Technologies AG
Kennedy Jennifer M.
Lerner Herbert L.
Niebling John F.
LandOfFree
Method for producing barrier-free semiconductor memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing barrier-free semiconductor memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing barrier-free semiconductor memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2546788