Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-16
2001-10-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S164000, C438S156000
Reexamination Certificate
active
06300198
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to a method for the production of a vertical MOS transistor.
2. Discussion of the Related Art
With a view to ever-faster components with higher integration density, the structural sizes of integrated circuits are decreasing from generation to generation. This is also true with regard to CMOS technology. It is generally expected (see, for example, Roadmap of Semiconductor Technology, Solid State Technology 3, 1995), that MOS transistors with a gate length of less than 100 nm will be used around the year 2010.
On the one hand, attempts have been made to scale modern CMOS technology in order to produce planar MOS transistors with such gate lengths (see, for example, A. Hori, H. Nakaoka, H. Umimoto, K. Yamashita, M. Takase, N. Shimizu, B. Mizuno, S. Odanaka, A 0.05 &mgr;m-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5 keV Ion Implantation and Rapid Thermal Annealing, IEDM 1994, 485 and H. Hu, L. T. Su, Y. Yang, D. A. Antoniadis, H I. Smith, Channel and Source/Drain Engineering in High-Performance sub-0.1 &mgr;m NMOSFETs using X-ray lithography, Symp. VLSI Technology, 17, 1994). The production of such planar MOS transistors with a channel length of less than 100 nm requires the use of electron beam lithography and has hitherto been possible only on a laboratory scale. The use of the electron beam lithography leads to a superproportional increase in development costs.
In parallel with this, vertical transistors have been investigated with a view to producing shorter channel lengths (see L. Risch, W. H. Krautschneider, F. Hofmann, H. Schäfer, Vertical MOS Transistor with 70 nm channel length, ESSDERC 1995, pages 101 to 104). In this case, layer sequences are formed corresponding to the source, channel and drain, and are annularly surrounded by the gate dielectric and gate electrode. In terms of their radio-frequency and logic properties, these vertical MOS transistors have to date been unsatisfactory in comparison with planar MOS transistors.
German patent no. 196 21 244 has proposed a MOS transistor with reduced stray gate capacitances, which is suitable for radio-frequency applications. In order to produce this vertical transistor, a mesa structure comprising a source region, channel region and drain region in vertical succession is formed on a semiconductor substrate. The gate electrode is formed in such a way that it adjoins the mesa structure only at the channel region. Oxide structures, which embed the gate electrode, are formed below and above the gate electrode at the source and drain regions. The gate capacitances are minimized in this way. In order to produce the oxide structures and the gate electrode, corresponding layers are respectively deposited which cover the mesa. Photoresist is applied on top and planarized. The photoresist is subsequently etched back to an extent that leaves free the upper sides of the mesa. This structured photoresist is subsequently used as a mask in order to structure the underlying layer at the mesa. The thickness of the layer is in each case less than the height of the mesa. Since the planarity is limited by the flow of planarized photoresist, the height of the etching erosion in the further structuring of the photoresist layer by etching is difficult to control.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method for the production of a vertical MOS transistor with reduced gate overlap capacitances, which is essentially improved with regard to process reliability.
This object is achieved in accordance with the invention in a method for producing a vertical MOS transistor having a mesa structure, which has a lower source/drain region, a channel region and an upper source/drain region, is formed from a semiconductor layer sequence. The semiconductor layer sequence is formed by epitaxy or by implantation and annealing. A first auxiliary layer, which is structured together with the semiconductor layer sequence, is applied to the semiconductor layer sequence. A terminal region for the lower source/drain region is formed laterally with respect to the mesa structure in the semiconductor substrate. An insulation structure is formed which essentially covers at least the side wall of the lower source/drain region. A gate dielectric and a gate electrode are formed on the side of the channel region. The height of the gate electrode is essentially equal to the height of the channel region. In order to form the insulation structure, an insulating layer is applied whose thickness is greater than or equal to the thickness of the semiconductor layer sequence. The insulating layer is planarized by chemical/mechanical polishing. In this case, the first auxiliary layer, which is located as the uppermost layer on the mesa structure, is used as an etching stop.
A flat zone, in which the surface of the first auxiliary layer is exposed, is formed by the chemical/mechanical polishing. This provides a reference plane for subsequent etching steps. The depth of the etching erosion in subsequent etching steps can therefore be controlled better than in the prior art.
According to one embodiment of the invention, the insulating layer is applied with essentially conformal edge coverage. Its thickness in this case is essentially equal to the thickness of the semiconductor layer sequence. This means that, laterally with respect to the mesa structure, the surface of the insulating layer is level with the surface of the upper source/drain region of the mesa structure.
A second auxiliary layer is applied which has the same etching properties and essentially the same thickness as the first auxiliary layer. Laterally with respect to the mesa structure, the surface of the second auxiliary layer is therefore arranged level with the surface of the first auxiliary layer. The second auxiliary layer is subsequently structured in such a way that the surface of the insulating layer is exposed at least in a first area, The first area laterally overlaps the mesa structure. The lateral dimensions of the first area are respectively greater by at least twice the layer thickness of the insulating layer than corresponds to the corresponding lateral dimension of the mesa structure. The second auxiliary layer therefore covers the insulating layer in the part which is arranged outside the mesa structure and in which the elevation of the mesa structure does not have an effect on the topology of the insulating layer. In other words: during the structuring of the second auxiliary layer, that part of the second auxiliary layer is removed in which the surface of the second auxiliary layer is arranged above the surface of the first auxiliary layer. After the structuring of the second auxiliary layer, the surface of the first auxiliary layer and the surface of the second auxiliary layer are arranged everywhere at the same level.
The surface of the first auxiliary layer is subsequently exposed by chemical/mechanical polishing of the insulating layer. The first auxiliary layer and the second auxiliary layer in this case act as an etching stop.
Subsequently, using the first auxiliary layer and the second auxiliary layer as a mask, the insulating layer is etched to such an extent that the side wall of the channel region is essentially exposed. The insulating layer is not etched underneath the channel region, so that, on the side wall of the mesa structure, the insulating layer extends as far as the boundary between the lower source/drain region and the channel region.
A gate dielectric is formed on the exposed side wall of the channel region.
A conductive layer is produced which essentially fills the intermediate space between the insulating layer and the mesa structure. The intermediate space between the insulating layer and the mesa structure is produced by the etching of the insulating layer as far as the upper boundary of the lower source/drain region. The gate electrode is subsequently formed by etching back the conductive layer.
The second auxiliary layer is preferably stru
Aeugle Thomas
Behammer Dag
Rosner Wolfgang
Elms Richard
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
Smith Bradley
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