Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-10
2004-08-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S391000, C438S424000
Reexamination Certificate
active
06770530
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module.
So-called shallow trench isolation (STI) is increasingly being used to isolate active regions on semiconductor modules. STI is used to an increased extent particularly in the more recent memory generations (starting with 16 M through to the present-day 512 M DRAM (Dynamic Random Access Memory) and in new generations of logic modules. The prior art process sequence for STI is that first a trench (shallow trench) is etched into the silicon substrate, and the trench is then partly filled with oxide (TEOS (Tetraethyl orthosilicate) or HDP (High Density Plasma)) and planarized until only the isolation oxide remains in the trench. A nitride liner, which was deposited before the oxide in order to protect the foundation during the further processing, is situated at the isolation edge of each transistor after the STI etching. Hitherto, a nitride liner has been fitted completely to all of the transistors. Although this has led to improved properties in the case of the n-channel transistors, during chemical mechanical polishing (CMP) potassium ions are deposited and shorten the channel, which, in the case of p-channel transistors, has resulted in a breakdown (punch-through) and a degradation of the p-channel transistors. Therefore, more recently the nitride liner has been completely dispensed with, although the positive effect on the n-channel transistors has been lost.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module, which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
In particular, it is an object of the invention to provide a method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module, which both exploits the advantages of a nitride liner for n-channel transistors and does not entail any impairment for p-channel transistors.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing shallow trench isolations for n-channel field-effect transistors and p-channel field-effect transistors in a semiconductor module. The method includes steps of: forming shallow trench isolation trenches in a substrate for the n-channel field-effect transistors and the p-channel field-effect transistors; applying an oxide layer; applying a nitride layer; producing a mask for covering regions in which the n-channel field-effect transistors will subsequently be formed; removing the nitride layer in regions not covered by the mask; and removing the mask.
In accordance with an added feature of the invention, the oxide layer is a thermal oxide layer.
In accordance with an additional feature of the invention, the method includes applying a further oxide layer between the oxide layer and the nitride layer.
In accordance with another feature of the invention, the further oxide layer is a high-density plasma tetraethyl orthosilicate layer.
In accordance with another added feature of the invention, the further oxide layer is applied thinner at walls of the shallow trench isolation trenches than on horizontal areas of the shallow trench isolation trenches.
In accordance with a further feature of the invention, step of producing the mask includes: applying a further oxide layer to the nitride layer; applying a resist mask in the regions in which the n-channel field-effect transistors will subsequently be formed; implanting N
2
into the further oxide layer in the regions not covered by the resist mask; removing the resist mask; and removing the further oxide layer implanted with the N
2
.
In accordance with a further added feature of the invention, step of producing the mask includes: applying a poly-Si layer to the nitride layer; applying a resist mask in the regions in which the n-channel field-effect transistors will subsequently be formed; implanting BF
2
into the poly-Si layer in regions not covered by the resist mask; removing the resist mask; and removing the poly-Si layer implanted with the BF
2
.
In accordance with another added feature of the invention, step of producing the mask includes: applying a further oxide layer to the nitride layer; applying a resist mask in the regions in which the n-channel field-effect transistors will subsequently be formed; removing the further oxide layer in regions not covered by the resist mask; and removing the resist mask.
In accordance with another additional feature of the invention, step of producing the mask includes: applying a poly-Si layer to the nitride layer; applying a resist mask in the regions in which the n-channel field-effect transistors will subsequently be formed; removing the poly-Si layer in regions not covered by the resist mask; and removing the resist mask.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing shallow trench isolations for n-channel field-effect transistors and p-channel field-effect transistors in a semiconductor memory module. The method include steps of: forming shallow trench isolation trenches in a substrate for the n-channel field-effect transistors and the p-channel field-effect transistors, the substrate being for producing the semiconductor memory module; applying an oxide layer; applying a nitride layer; producing a mask for covering regions in which the n-channel field-effect transistors will subsequently be formed; removing the nitride layer in regions not covered by the mask; and removing the mask.
In accordance with an added feature of the invention, the substrate is for producing a dynamic random access memory.
The inventive solution results in an improvement in the storage duration of the memory cells and an increase in the threshold voltage of the selection transistor, which reduces a cell-to-bitline leakage.
According to the invention, the following steps are performed in order to produce a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module. An oxide layer and, above the oxide layer, a nitride layer are applied in isolation trenches present on a substrate. Afterward, a masking is applied and the nitride layer is removed in accordance with the masking. Finally, the masking is also removed.
The following steps are performed in accordance with a preferred embodiment of the inventive method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module. A first oxide layer is applied in isolation trenches present on a substrate. A further oxide layer and a nitride layer are subsequently applied. In a further step, a mask is applied in the region in which an n-channel field-effect transistor is intended to be produced. The nitride layer is removed around the mask. Finally, the mask is also removed.
The following steps are performed in accordance with a further preferred embodiment of the method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module. An oxide layer and a nitride layer and, above the nitride layer, a further oxide layer or a poly-Si layer are applied in isolation trenches present on a substrate. Afterward, a resist mask is applied and the further oxide layer or the poly-Si layer is removed in accordance with the resist mask. In a further step, the nitride layer is likewise removed in the region in which the further oxide layer or the poly-Si layer has been removed.
In accordance with a further preferred embodiment of the method for producing a shallow trench isolation for n- and p-channel field-effect transistors, in order to produce the masking, a further oxide layer or a poly-Si layer is applied to the nitride layer. In a region in which n-channel field-effect transistors are
Efferenn Dirk
Moll Hans-Peter
Wich-Glasen Andreas
Lee Calvin
Smith Matthew
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