Method for producing a memory cell

Details Method for producing a memory cell Method for producing a memory cell

1998-02-09

2001-09-18

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000

Reexamination Certificate

active

06291287

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for producing a memory cell in an integrated circuit starting from a whole-area silicon layer on a dielectric.
Memory cells are EEPROMs and flash EEPROMs. The silicon layer may be monocrystalline, polycrystalline or amorphous silicon. The dielectric which is used is usually silicon dioxide, for example as a gate oxide, or silicon nitride.
In the production of memory cells of that type, a polysilicon layer for a following structuring on a dielectric is generally produced in the course of the first method steps. The desired structuring, in particular of transistor gates, is carried out through the use of photolithography. The etching processes which are used in that case make very high requirements of the photoresist. The wet-chemical etching processes, in particular, produce relatively large, greatly varying undercuts and lead, in principle, to concave polysilicon edges which can only be treated with difficulty from the standpoints of production engineering and planarization.
In polysilicon etching processes, there is the risk of the gate oxide situated under the polysilicon becoming damaged. Since, moreover, the selectivity between the polysilicon and the silicon oxide is insufficient during etching, in a manner dictated by the system, the gate oxide is thinned in an unreproducible manner outside the gate regions in the source/drain regions which are to be produced later, with the result that the gate oxide, for defined source/drain implantation, has to be completely removed and replaced by an oxide that is to be newly formed. That necessitates a further wet-chemical etching process.
The last-mentioned etching produces a hollow groove in the gate oxide under the polysilicon gate edge, which produces a nonhomogeneous, difficult-to-control transition from the gate to the source/drain region with corresponding yield and reliability risks for the transistor. With regard to cleaning and to the oxidation behavior, such a hollow groove can only be controlled with difficulty in terms of process engineering. In particular, the insulation strength of an insulation oxide, formed thereon, with respect to a second polysilicon layer, for example in an EEPROM process, is adversely influenced by this fact.
Furthermore, for the purpose of producing MOS transistors, German Published, Non-Prosecuted Patent Application 27 39 662 discloses covering the silicon layer with a layer which serves as an oxidation protection, structuring the oxidation protection layer through the use of photolithography in order to produce a mask through the use of etching the oxidation protection layer and uncovering the polysilicon in the unmasked regions, and converting the polysilicon in the uncovered regions into silicon dioxide through the use of local oxidation.
IEEE Transactions on Electron Devices, Vol. ED 28, No.1, January 1981, pages 77-82 and Vol. ED 31, No.10, October 1984, pages 1413 to 1419 describes the production of a MOS circuit and of an EPROM. Furthermore, Published Japanese Patent Application 57-42169 and Published European Patent Application 0 294 699 A2 describe methods for producing memory cells. However, a relatively large number of method steps are required for producing a dielectric.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for producing a memory cell, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and which is simple.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing a memory cell having a transistor and a capacitor in an integrated circuit, which comprises initially providing a whole-area polysilicon layer; covering the polysilicon layer with an oxidation protection layer; structuring the oxidation protection layer by photo-lithography to produce a mask covering a gate region and a field region of the transistor by etching the oxidation protection layer and uncovering the polysilicon in unmasked regions, causing the oxidation protection layer remaining over the field region to form a dielectric and the underlying polysilicon to form a first electrode of the capacitor; converting the polysilicon of the polysilicon layer in regions freed from the oxidation protection layer into silicon dioxide by local oxidation; applying a further polysilicon layer with an inclusion of a remaining oxidation protection layer; applying and structuring a photoresist mask to cover a region of the further polysilicon layer disposed above the field region for forming a second electrode of the capacitor; producing the second electrode of the capacitor by etching the further polysilicon layer in the unmasked regions; and if appropriate removing the oxidation protection layer in regions not required for a remainder of the production process.
A basic concept of the invention may thus be seen in the fact that the structuring of the polysilicon, that is to say the removal of unnecessary polysilicon areas, is achieved not by conventional etching, but by conversion into silicon dioxide. The invention has the advantage of causing no gate oxide overetching and no associated hollow groove formation under the polysilicon edge to arise, with the result that a homogeneous transition in the gate oxide from the gate region to the source/drain region is provided in the case of MOS transistors. Furthermore, the polysilicon side edge is completely embedded in a homogeneously grown oxide having a thickness which corresponds approximately to at least that of the polysilicon. The insulation strength with respect to an optionally superior, second polysilicon layer, as in the case of an EEPROM, for example, is thereby determined only by the planar and therefore easy-to-control thickness of the nitride layer originally serving as a structuring mask for the first polysilicon layer or, if appropriate, of a different dielectric, since the limiting influence of the polysilicon edge is no longer present.
Furthermore, the invention avoids the disadvantage existing with conventional methods in the case of MOS transistors, in which a process-dictated abrupt transition in the gate oxide thickness at the gate edge from the gate to the source/drain region leads to a locally higher field strength between the gate edge and the source/drain region. Instead, a steady increase in the gate oxide thickness at the transition from the gate to the source/drain region is produced by the oxidation process. This avoids local field strength peaks with the consequence of amplified degradation of the transistor parameters in this critical region. The transistor reliability is increased in this way, in particular at higher operating voltages of the kind which are customary in EEPROM applications, for example.
Since the polysilicon edge produced by the oxidation according to the invention has a convex profile, this convex gate edge also contributes to avoiding the local field strength peaks and thus to better transistor reliability.
Furthermore, the invention achieves a sufficiently high breakdown voltage of the source/drain regions, which is very advantageous, for example, in EEPROM applications again. In combination processes, for example in the production of so-called embedded memories, it is therefore possible for source/drain regions of low-voltage logic transistors that are usually produced at a later point in time to be independently produced and optimized with fewer requirements on the dielectric strength. In the production of MOS transistors, it is advantageous that before the removal of the photoresist mask used during the photolithography, the source/drain implantation is effected through the uncovered silicon. The small doping gradient, which is responsible for the high breakdown voltage, of the source/drain diffusion for EEPROM applications, for example, is based on the fact that the implantation takes place relatively at the beginning of the entire production process and before the oxidation

Affiliated with

Also associated with

Rating

Method for producing a memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for producing a memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing a memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2545003