Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-22
2001-03-20
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S655000
Reexamination Certificate
active
06204129
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integration of high-voltage and low-voltage MOS transistors, and more particularly, to a method for producing high-voltage and low-voltage salicide process.
2. Description of the Prior Art
As the scale of integrated circuits (ICs) has been rapidly decreased, the design and layout rule becomes more stringent. Moreover, as the integrated circuits (ICs) are fabricated to be more compact, the integration of ICs with different application becomes indispensable.
In the conventions, the integration of the high-voltage and low-voltage MOS transistors are majoring used to polycide process without salicide process. The great of reasons are
for the sake to strengthen the ability of junction breakdown in high-voltage MOS transistor, the N
+
-type region to polysilicon layer of gate has N-type grade area, while implanting the energy with N-type ions into the grade is usually considerably height (>100 KeV). Therefore, according to the old tradition of the salicide process of polysilicon layer with the gate, the high energy of implanting N-type grade is embedded in the channel under polysilicon layer of result in the shift of threshold voltage of high-voltage MOS transistor.
the silicidation region is not formed above the top surface of N-type grade region. If the silicidation region is formed, the current will flow along the upper surface with silicidation region to reduce the ability of junction breakdown.
FIGS. 1A and 1B
shows the cross section of a conventional high-voltage and low-voltage MOS transistors, which usually includes a silicon substrate
100
, field oxide regions
120
, an N
+
-type source/drain region
160
of high-voltage and low-voltage MOS transistors, a polysilicon layer
140
, and a WSi layer
200
. Then, the N-type grade region is only formed in the substrate of high-voltage MOS transistor. In the structure of the shown transistor, the silicidation region of the structure is not formed above the top surface of N-type grade region. If the silicidation region is formed, the current will flow along the upper surface with silicidation region to reduce the ability of junction breakdown.
For the foregoing reasons, there is a need for disclosing a structure and a method of fabricating high-voltage and low-voltage MOS transistors having self-aligned silicidation.
SUMMARY OF THE INVENTION
An object of the present invention is to substantially obviate one or more of the problems caused by limitations and disadvantages of the related art.
In accordance with the present invention, a method is provided for producing self-aligned silicidation of the high-voltage and low-voltage MOS devices, substantially facilitating the integration of the high-voltage and low-voltage MOS devices. Owing to the use of a method, so that the provided self-aligned silicidation process in the high-voltage and low-voltage MOS device can be adapted quality fabrication.
Another purpose of the present invention is to provide a silicon nitride layer on the gate, thereby avoiding the channeling effect of the implanting N-type grade.
Moreover, the present invention provides a high-voltage and low-voltage MOS transistor with N
+
mask design, thus enhancing self-aligned silicidation process in high-voltage and low-voltage MOS transistors.
In the embodiment, the present invention provides an integration of high-voltage and low-voltage MOS transistors, which have self-aligned silicidation process. A substrate is provided incorporating a device, wherein the device is defined high-voltage MOS region and low-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxide is spaced from another of the field oxide by a MOS region. Moreover, a polysilicon layer is formed above said high-voltage MOS region and low-voltage MOS region, and a first dielectric layer is deposited above the polysilicon layer of the high-voltage MOS region and low-voltage MOS region. Consequently, a first photoresist layer is formed over the first dielectric layer, wherein defining and etching the first photoresist layer to form gates of high-voltage MOS and low-voltage MOS. Then, using said second photoresist layer as a mask above low-voltage MOS region, firstly implanting the substrate of the high-voltage MOS region to form conductivity-type grade therein, and then the second photoresist layer of low-voltage MOS region is removed. . Moreover, spacers are formed on sidewall of said gates of high-voltage MOS and low-voltage MOS, and then a second dielectric layer is formed on the substrate of high-voltage MOS and low-voltage MOS. Subsequently, a third photoresist layer having a first pattern is formed on high-voltage MOS and a second pattern on the low-voltage MOS, wherein etching a portion of the first dielectric layer and the second dielectric layer until top surface of the polysilicon layer and the grade is exposed by using the third photoresist layer as a hard mask. Moreover, second conductivity type ions are implanted into the grade region of high-voltage MOS and into the substrate of low-voltage MOS using the third photoresist layer as a mask, and then the third photoresist layer is removed. Finally, the exposed polysilicon layer and the grade are sputtered to form silicide region.
REFERENCES:
patent: 6008077 (1999-12-01), Maeda
patent: 6010929 (2000-01-01), Chapman
patent: 6077736 (1999-12-01), Hwang et al.
Chen Wei-Chung
Hwang Ching-Chun
Yang Chien-Kuo
Chaudhari Chandra
United Microelectronics Corp
LandOfFree
Method for producing a high-voltage and low-voltage MOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing a high-voltage and low-voltage MOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing a high-voltage and low-voltage MOS... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2523034