Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-05-03
2005-05-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S530000
Reexamination Certificate
active
06887764
ABSTRACT:
In a method for producing a gate structure for a MOS transistor, first, a layer sequence of oxide layer, auxiliary layer and masking layer is generated on a substrate, wherein the auxiliary layer and the masking layer are patterned to determine an edge separating an area of the oxide layer covered by these layers from an exposed area thereof. Afterwards, an oxidation is performed to generate an oxide ramp in the area of the edge. Then, the auxiliary layer is partly removed to generate a hollow space of predetermined length between the oxide layer and the masking layer. A gate electrode material is introduced into the hollow space for generating a gate electrode.
REFERENCES:
patent: 4952525 (1990-08-01), van der Plas
patent: 5424227 (1995-06-01), Dietrich et al.
patent: 5741737 (1998-04-01), Kachelmeier
patent: 5817536 (1998-10-01), Nayak et al.
patent: 5858844 (1999-01-01), Fang et al.
patent: 6136657 (2000-10-01), Yang et al.
patent: 6225162 (2001-05-01), Lin et al.
patent: 6281079 (2001-08-01), Heineck et al.
patent: 20040185646 (2004-09-01), Herzum
patent: 198 12 212 (1999-09-01), None
patent: 101 31 917 (2003-01-01), None
Herzum Christian
Mueller Karlheinz
Lindsay Jr. Walter L.
Maginot Moore & Beck
Niebling John F.
LandOfFree
Method for producing a gate structure for an MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing a gate structure for an MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing a gate structure for an MOS transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3398896