Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-06-28
2011-06-28
Hoang, Quoc D (Department: 2894)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S317000
Reexamination Certificate
active
07968398
ABSTRACT:
A diblock copolymer layer comprising at least two polymers and having a lamellar structure perpendicularly to a substrate is deposited on a first gate insulator formed on the substrate. One of the polymers of the diblock copolymer layer is then eliminated to form parallel grooves in the copolymer layer. The grooves are filled by a first metallic or semi-conductor material and the rest of the copolymer layer is eliminated. A second dielectric material is deposited to form a second gate insulator. The second gate insulator of the floating gate then comprises an alternation of parallel first and second lines respectively of the first and second materials, the second material encapsulating the lines of the first material.
REFERENCES:
patent: 7045851 (2006-05-01), Black et al.
patent: 2003/0193064 (2003-10-01), Wu
patent: 2004/0256662 (2004-12-01), Black et al.
patent: 2005/0287717 (2005-12-01), Heald et al.
patent: 2008/0193658 (2008-08-01), Millward
Baron et al., “Nucleation control of CVD growth silicon nanocrystals for quantum devices,”Microelectronic Engineering, vol. 61/62, pp. 511-515, Jul. 1, 2002.
Park et al., “Directed Assembly of Lamellae-Forming Block Copolymers by Using Chemically and Topographically Patterned Substrates,”Advanced Materials, vol. 19, pp. 607-611, 2007.
Mansky et al., “Controlling Polymer-Surface Interactions with Random Copolymer Brushes,”Science, vol. 275, pp. 1458-1460, Mar. 7, 1997.
Tan et al., “Hafnium Aluminum Oxide as Charge Storage and Blocking-Oxide Layers in SONOS-Type Nonvolatile Memory for High-Speed Operation,”IEEE Transactions on Electron Devices, vol. 53, No. 4, pp. 654-662, Apr. 2006.
Chin et al., “Low Voltage High Speed SiO2/AlGaN/AlLaO3/TaN Memory with Good Retention,”Electron Devices Meeting, IEDM Technical Digest, pp. 158-161, Dec. 5-7, 2005.
Wang et al., “Long Retention and Low Voltage Operation Using IrO2/HfAlO/HfSiO/HfSiO/HfAlO Gate Stack for Memory Application,”Electron Devices Meeting, IEDM Technical Digest, pp. 162-165, Dec. 5-7, 2005.
Aissou Karim
Baron Thierry
Molas Gabriel
Centre National de la Recherche Scientifique
Commissariat a l''Energie Atomique
Hoang Quoc D
Oliff & Berridg,e PLC
Tran Tony
LandOfFree
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