Method for producing a DRAM cellular arrangement

Details Method for producing a DRAM cellular arrangement Method for producing a DRAM cellular arrangement

1999-03-15

2000-03-14

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, 438396, H01L 218242

Patent

active

060372095

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates generally to a method for producing a DRAM cell including a vertical transistor.
2. Description of the Related Art
In DRAM cell arrangements, that is to say memory cell arrangements with dynamic random access, use is made almost exclusively of so-called single-transistor memory cells. A single-transistor memory cell comprises a read-out transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge, which represents a logic value, zero or one. By driving the read-out transistor via a word line, this information can be read out via a bit line.
Since the storage density increases from memory generation to memory generation, the required area of the single-transistor memory cell must be reduced from generation to generation. Since limits are imposed on the reduction of the structure sizes by the minimum structure size F which can be produced using the respective technology, this is also associated with an alteration of the single-transistor memory cell. Thus, up until the 1 Mbit generation, both the read-out transistor and the storage capacitor were realized as planar components. Starting with the 4 Mbit memory generation, a further reduction in area had to be effected by means of a three-dimensional arrangement of the read-out transistor and the storage capacitor. One possibility is to realize the storage capacitor in a trench (see, for example K. Yamada et al., A deep trenched capacitor technology for 4 Mbit DRAMs, Proc. Intern. Electronic Devices and Materials IEDM 85, page 702).
Furthermore, it has been proposed (see, for example, Y. Kawamoto et al., A 1,28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64 Mbit DRAMs Techn. Digest of VLSI Symposium 1990, page 13) to design the storage capacitor as a so-called stacked capacitor. In this case, a polysilicon structure, for example a crown structure or a cylinder, is formed over the word lines and makes contact with the substrate. This polysilicon structure the storage node. It is provided with a capacitor dielectric and capacitor plate. This concept has the advantage that it is largely compatible with a logic process.
The area for a memory cell of a DRAM belonging to the 1 Gbit generation should only be about 0.2 .mu.m.sup.2. At the same time, the storage capacitor must have a capacitance of 20 to 30 fF. In the case of a cell area such as is available in the 1 Gbit generation, such a capacitance is feasible in a stacked capacitor only with a relatively complicated structure of the polysilicon structure. These complicated structures are more and more difficult to produce, in addition, due to their topology.
Furthermore, it has been proposed to increase the capacitance which can be achieved per area by using a dielectric having a high dielectric constant. Paraelectric and ferroelectric materials, in particular, are suitable as dielectric having a high dielectric constant (see Published PCT application no. WO 93/12542), for example).
The present invention is based on the problem of specifying a method for the production of a DRAM cell arrangement whose memory cells comprise single-transistor memory cells, by means of which method it is possible to achieve the component density which is necessary for the 1 Gbit generation.
This problem is solved by a method for the production of a DRAM cell arrangement.
in which a first mask layer and a second mask layer, which can be etched selectively with respect to one another, are applied to a semiconductor substrate comprising a first layer which is doped by a first conductivity type, a second layer, which is doped by a second conductivity type opposite to the first, and a third layer, which is doped by the first conductivity type and adjoins a main area of the semiconductor substrate,
in which the second mask layer and the first mask layer are structured jointly,
in which the structured first mask layer is etched back under the structured second mask layer by means of sel

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S. Maeda et al., IEEE Transactions on Electron Devices, vol. 42, No. 12, Dec. 1995, pp. 2117-2124.
Y. Kawamoto et al., 1990 Symposium on VLSI Technology, pp. 13-14.
Japanese Abstract, Publication No. 60021558.
K. Yamada et al., "A Deep-Trenched Capacitor Technology for 4 Mega Bit Dynamic Ram", IEDM 85, pp. 702-705.

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