Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-04-25
2001-01-16
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S088000, C438S745000, C438S756000
Reexamination Certificate
active
06174814
ABSTRACT:
TECHNICAL FIELD
The present invention is directed generally to the manufacture of integrated circuits and, in particular, to the prevention of cracking and crack propagation in the dielectric materials that surround underlying circuit elements.
BACKGROUND OF THE INVENTION
In the course of manufacturing an integrated circuit, common practice is to first develop desired semiconductor circuit elements and the corresponding interconnections on an appropriate substrate, followed by the application of a dielectric material over the resulting structure for purposes of protecting the relatively fragile underlying elements. This is conventionally followed by a process for leveling irregularities in the dielectric overlayer to restore topological planarity to the manufactured component. Chemical-mechanical polishing (CMP) of the surface of the applied dielectric material is commonly used for such purposes.
Chemical-mechanical polishing has a disadvantage, however, in practice: the CMP process can itself damage or scratch the surface of the wafer being formed. Scratches can occur, for example, by dragged or rolling contact from particles present in the polishing pad, from the polishing slurry, or from the wafer itself. Cracks can be nucleated and initiated from such scratches or other particle contacts and propagated by tension in the wafer arising from CMP fixturing, and the stress-corrosive properties of the reactive CMP solution. The analysis of manufactured complementary metal-oxide-semiconductor (CMOS) products has revealed that scratches can lead to cracks propagating downwardly through one or more of the layers positioned beneath the polished surface.
For example, in manufacturing CMOS products, it has been found that a scratch occurring during the metal conductor/glass CMP step can initiate a crack that propagates through several layers of material, including the gate stack (which is itself a very brittle structure). Electrically, such a crack can be detected as an “open” gate. Analysis of such failures (using a scanning electron microscope) reveals that such cracking can dislocate the gate stack leading to a physical break in the gate, which prevents current from passing through the structure. Although the scratch can be partially removed from the surface layer by subsequent polishing, the crack has already damaged the lower layers of the manufactured article.
Therefore, the primary object of the present invention is to prevent cracks initiated in the surface of a dielectric material from propagating downwardly, into the underlying layers of a manufactured integrated circuit. Another object of the present invention is to prevent cracks initiated in the surface of a dielectric material from propagating downwardly, into underlying layers, in a way that is fully compatible with the existing processes used to manufacture integrated circuits, and that itself requires the use of a minimal number of additional manufacturing steps.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides an interface between the outermost (dielectric) layer or layers and the inner layer or layers forming the integrated circuit so that cracks resulting from scratches formed in the surface of the dielectric material are prevented from propagating through to the inner layer or layers.
The improvements of the present invention can be implemented by depositing a layer of a “dissimilar material” (e.g., a polymer such as polyimide, or a material having equivalent properties) over the inner layer or layers forming the integrated circuit, followed by the conventional application of an outer, dielectric layer (e.g., silicate glass). As a result, during subsequent CMP processing, a crack formed in the surface of the dielectric only propagates through the outer, dielectric layer, stopping or arresting at or in the dissimilar layer. Different sequences of dielectric layers can be used, if desired, to achieve still further improvements (e.g., a tri-layer structure including the layers glass/dissimilar material/glass, or with the dissimilar material deposited or applied first, becoming the bottom layer).
Selection of the dissimilar material in general depends on the thermal and dielectric properties of the material, as well as its mechanical properties. The thermal properties of the dissimilar material must be compatible with the subsequent processing (integration) steps. The dielectric properties must further meet the reliability and performance requirements for the product. The mechanical properties will determine if the material is capable of preventing a crack from propagating, in effect producing an interlevel crack stop.
It has been suggested previously to insert a layer of material in the oxide layer and over the gate, in order to protect the gate, by arresting the potential crack in the inserted material. For example, Japanese Patent No. 7-86284 discloses the placement of a layer of spin-on glass (SOG) over the gate structure of a semiconductor device in order to arrest the crack in the SOG layer. U.S. Pat. No. 5,246,884 discloses the use of carbon-rich materials such as chemical vapor deposition (CVD) diamond-like carbon (DLC) overlayer etch stop. Materials such as SOG and DLC are themselves relatively brittle, however, and tend to facilitate the propagation of cracks rather than to prevent their propagation.
The use of a polymer such as polyimide as a crack stop layer has been found to be effective for various reasons. For example, it has been found that when a crack enters a layer of the polyimide material, which is somewhat plastic, propagation of the crack will be resisted due to energy absorption within the new material provided that a sufficiently thick layer is used. To make use of such a mechanism (i.e., energy absorption due to plasticity), it is necessary to use a relatively soft material, such as polyimide. In practice, however, there is a reluctance to incorporate materials such as polyimide into the body of a wafer for reasons of reliability.
In accordance with the present invention, it has further been found that some materials and processes can serve as an effective crack stop layer because the properties of the interface formed with the inserted material layer or by the inserted process tend to cause a crack that encounters the interface to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that is harmful to the manufactured article. This has been found to result from the presence of a lateral weakness at this interface, that diverts the propagation of the crack along the weakened interface rather than by arrest of the crack at or in an inserted layer. Moreover, it has been found that this effect can be achieved with materials other than polyimide, including materials that are more compatible with, and preferred for use in, the manufacture of integrated circuit components. Such effects are generally achievable with any interface having a lateral weakness responsive to crack propagation.
The present invention is primarily directed to the use of multiple layers of material, each of which is sufficiently thick to perturb a crack (e.g., a minimum thickness of about 50 Å). A main attribute of the present invention is the presence of multiple interfaces, each of which serves to horizontally deflect a propagating crack. Control of the fracture resistance of the interface is important because, the weaker the interface, the more likely that the crack will deflect along the interface. In practice, however, if the interface is made too weak, the resulting (layered) structure will not hold during the manufacturing process. Accordingly, there will generally be an optimum range for the fracture resistance of the interface, depending on the materials incorporated.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 4536251 (1985-08-01), Chiang et al.
p
Cook Robert F.
Garcia Eduardo
Greco Nancy A.
Greco Stephen E.
Levine Ernest N.
Anderson, Esq. Jay H.
International Business Machines - Corporation
Powell William
Ratner & Prestia
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