Method for preventing silicon substrate loss in fabricating...

Details Method for preventing silicon substrate loss in fabricating... Method for preventing silicon substrate loss in fabricating...

1999-02-25

2001-03-27

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S258000

Reexamination Certificate

active

06207491

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for preventing silicon substrate loss in fabricating a semiconductor device, and more particularly, to a method for reducing leakage current of the semiconductor device by preventing silicon substrate loss in fabricating a semiconductor device containing a periphery circuit and a memory cell.
2. Description of the Prior Art
A typical DRAM contains a periphery circuit region and a memory cell region. In fabricating a substrate is provided for fabricating the periphery circuit and a memory cell. The periphery circuit includes a row decoder, a column decoder, a refresh amplifier, a buffer, a register, a controller circuit, and a clock. The memory cell includes a transistor and a capacitor. All the forgoing devices in the memory cell region and the periphery circuit region are fabricated on the same substrate.
The leakage current of the device in the DRAM will result in serious problems such as frequent refresh operation to keep capacitors stored in capacitor of DRAM. Especially when fabricating the bit line or bit line in the memory cell region, the substrate loss is often resulted. The leakage current resulted from the substrate loss during fabricating the devices in the memory cell region is a problem caused by fabricating the semiconductor device.
As shown in
FIG. 1
, a gate structure
100
is formed on the substrate
101
. The gate structure
100
includes the gate oxide layer
100
a,
a gate polysilicon layer
100
b,
and a gate silicide layer
100
c.
In addition, a control line structure
104
and a control gate structure
105
are formed on the substrate
101
. Then a dielectric layer
110
is formed on the substrate, the gate structure
101
, a control line structure
104
, and a control gate structure
105
. To form the spacer at the side-wall of the gate structure
100
, an etch back process is utilized to anisotropically etch the dielectric layer
110
. Because the silicon loss can not be avoided when etching the dielectric layer
110
to form the spacer, the silicon loss occurs on the whole surface of the exposed substrate
101
.
Next, refer to
FIG. 3
, a photolithography process and an ion implantation step are subsequently used to form the source region
111
and drain region
112
. When the photolithography process mentioned above is utilized to form the source and drain region in the periphery circuit region
115
, a mask covering memory cell region is used to prevent the memory cell region
116
from implanting. After the forgoing step, traditional processes are utilized to fabricate the DRAM cell. Turning to
FIG. 3
, the gate structure
100
together with the etched dielectric layer
110
are used as the gate electrode of the transistor in the periphery circuit region
115
. In the other respect, the control line structure
104
and the control gate structure
105
are in the memory cell region
116
of the substrate
101
. Due to the global etching back performed to etch the dielectric layer
110
, the silicon loss occurs on the exposed surface of the substrate
101
including the periphery region
115
and the memory cell region
116
. Because the silicon loss occurred in the memory cell region
116
, the leakage current will be resulted in the memory cell region.
SUMMARY OF THE INVENTION
Because the silicon substrate loss in the memory cell region will result in the leakage current in the memory device such as a DRAM. The present invention discloses a method for eliminating leakage current in a semiconductor device by preventing silicon loss in a memory cell region of a substrate during fabricating the memory device.
The method according to the preferred embodiment of the present invention includes the following steps. Firstly, form a first gate structure on a periphery circuit region of the substrate, and form a first structure together with a second structure on the memory cell of the substrate. Then form a dielectric layer on the topography of the wafer. Next, etch the dielectric layer until the thickness is about 200-1000 angstroms. Subsequently, form a photoresist pattern on the memory cell region, and etch the exposed second portion of the dielectric layer to form spacers of the first gate structure. The spacers and the first gate structure mentioned above constitute a gate electrode of a first transistor.
Next, form a source region and a drain region in the substrate, wherein the gate electrode, the source region, and the drain region constitute a first transistor, then remove the photoresist pattern. Finally, form a second transistor, a capacitor, and a control line in the first area of the substrate, wherein the first structure and the second structure is formed on the first area of the substrate. The charges stored in the capacitor are addressed and controlled by the second transistor, the control line, and the first transistor.


REFERENCES:
patent: 5324680 (1994-06-01), Lee et al.
patent: 5907779 (1999-05-01), Choi
patent: 5935875 (1999-08-01), Lee
patent: 5969395 (1999-10-01), Lee
patent: 5970335 (1999-10-01), Helm et al.
patent: 6022776 (2000-02-01), Lien et al.

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