Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-01-31
2003-09-30
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S683000, C438S664000, C438S655000, C438S653000, C438S299000
Reexamination Certificate
active
06627525
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to prevention of polycide gate spiking, and more particularly relates to a method for preventing spiking phenomena that is induced by barrier/silicide layer that is formed by the sputtering method.
2. Description of the Prior Art
As shown in
FIG. 1A
, in order to overcome disadvantages of polycide gate such as poor adhesion between silicide layer
14
and polysilicon layer
12
, barrier layer
13
is used to connect silicide layer
14
and polysilicon layer
12
. Herein, one important function of barrier layer
13
is to prevent reaction and interaction between metal of silicide layer
14
and polysilicon layer
12
, and then to prevent occurrence of spiking phenomena. If occurrence of spike
15
is not properly prevented, as shown in
FIG. 1B
, quality of interface between silicide layer
14
and polysilicon layer
12
is degraded by directly contact, and more seriously, quality of dielectric layer
11
, such as silicon dioxide layer, or even quality of substrate
10
also is degraded.
However, as shown in
FIG. 1C
, because barrier layer usually is formed by sputtering method in well-known technology (such as silicon nitride formed by sputtering method), structure of barrier layer is limited by available ability of sputtering method. As a result, structure of barrier layer
131
is not uniform but is an assemble of many grains where shape of each gain is column type. Obviously, interstices between adjacent grains provide channels where metal of silicide layer
14
penetrates through to polysilicon layer
12
, and then barrier layer
131
can not effectively prevent occurrence of spike
15
.
Certainly, chemical vapor deposition (CVD) method also is a popular method for forming barrier layer
13
, and spike
15
is effectively prevented by barrier layer
13
that is formed by CVD method for structure of barrier layer
13
is uniform and number of interstice is neglectable. In contrast, stress between barrier layer
13
and polysilicon layer
12
is larger when barrier layer
13
is formed by CVD method, and then disadvantages such as peeling are unavoidable. In short, disadvantage of spikes is replaced by disadvantage of large stress and quality of polycide gate still is bad.
Moreover, silicide layer
14
also usually is formed by the sputtering method, and then structure of silicide layer
14
is amorphous. Because distribution of metal is non-uniform over amorphous silicide layer
14
and thickness of barrier layer
13
is decreased as size of total polycide gate is decreased, the opportunity that metal of silicide layer
14
penetrates into polysilicon layer
12
is increased when scale of semiconductor device is substantially decreased, especially when thermal diffusion is enhanced by any thermal process. Thus, spike phenomena is an unavoidable result under part of amorphous silicide layer
14
where proportion of metal is larger than other part of amorphous layer
14
.
Accordingly, it is obvious that disadvantages of spike phenomena are unavoidable whenever sputtering method is used to form polycide gate. Then, because application of sputtering method is an almost indispensable, it is desired to develop an effective method for preventing occurrence of spiking.
SUMMARY OF THE INVENTION
The primary object of the invention is to provide a method for preventing the spiking phenomena of a polycide gate.
Another object of the invention is to present a method that prevents spiking phenomena by reconstructing structure of barrier layer/silicide layer.
A further object of the invention is to present a practical and simple method for preventing spiking phenomena.
In order to achieve previous objects of the invention, a preferred embodiment of the present method comprises the following essential steps: forming an oxide layer on a substrate; forms a polysilicon layer on the oxide layer; sputtering a barrier layer on the polysilicon layer; performing a first rapid thermal process; sputtering a silicide layer on the barrier layer; performing a photolithography process and an etching process to remove part of the silicide layer, part of the barrier layer and part of the polysilicon layer to form a polycide gate; and performing a second rapid thermal process.
Further, it is emphasized that the invention can be expanded such that only one rapid thermal process applied. Neither rapid thermal processes use oxygen.
Obviously, main spirit of the invention is to cover the conductor plug by plasma enhanced tetraethyl-orthosilicate layer that structure is compacted and deposit rate is high, and then some disadvantages of well-known technology are overcame.
REFERENCES:
patent: 5874353 (1999-02-01), Lin et al.
patent: 5981320 (1999-11-01), Lee
patent: 6136636 (2000-10-01), Wu
patent: 6187674 (2001-02-01), Chen et al.
patent: 6281052 (2001-08-01), Shinmura
Chen Ming-Tsung
Hsu Kirk
Jung Le-Tien
Dickinson Wright PLLC
Jr. Carl Whitehead
Nguyen Thanh
United Microelectronics Corp.
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