Method for preventing low-k dielectric layer cracking in...

Details Method for preventing low-k dielectric layer cracking in... Method for preventing low-k dielectric layer cracking in...

2005-01-25

2005-01-25

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Radiation or energy treatment modifying properties of...

Ionized irradiation

Reexamination Certificate

active

06846756

ABSTRACT:
A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.

REFERENCES:
patent: 6472333 (2002-10-01), Xia et al.
patent: 6503829 (2003-01-01), Kim et al.
patent: wo 2001045154 (2000-12-01), None
patent: WO 2003005429 (2003-11-01), None
patent: WO 2002016477 (2001-08-01), None
Fayolle, M. et al., “Integration of Cu/SioC in CU Dual Damascene Interconnect For 1-mum Technology”, Journal, vol. 64 (1-4), pp. 35-42 2002.

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