Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-22
2003-05-20
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S276000, C438S199000, C438S302000, C438S786000, C438S514000, C438S525000
Reexamination Certificate
active
06566203
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of performing a pocket implantation process to a nitride read only memory (NROM), and more particularly, to a method of preventing electron secondary injection in the pocket implantation process.
2. Description of the Prior Art
Nitride read only memory (NROM) is a semiconductor device used to store data, which is composed of a plurality of memory cells. Each memory cell comprises a control gate and a gate dielectric layer of oxide-nitrogen-oxide (ONO) structure. Because the silicon nitride layer of the ONO layer is highly compact, hot electrons injecting through tunneling oxide into the silicon nitride layer are trapped. As a result the silicon nitride layer may be used as a floating gate for storing data.
Please refer to
FIG. 1
to FIG.
6
.
FIG. 1
to
FIG. 6
are cross-sectional diagrams of a method of forming an NROM cell according to the prior art. As shown in
FIG. 1
, an NROM cell is formed on the surface of a P-type silicon substrate
10
. The prior art method first performs an ONO process on the surface of the P-type silicon substrate
10
to form an ONO dielectric layer
18
composed of a bottom oxide layer
12
, a silicon nitride layer
14
and a top oxide layer
16
. A photolithographic process is employed to form a photoresist layer
20
on the surface of the ONO dielectric layer
18
. The photoresist layer
20
forms patterns to define positions of bit lines.
As shown in
FIG. 2
, the photoresist layer
20
is used as a mask for performing an anisotropic etching process to remove the top oxide layer
16
and the silicon nitride layer
14
not covered by the photoresist layer
20
. Following that, an ion implantation process
22
is performed to form a plurality of N-type doped areas
24
in the silicon substrate
10
that function as bit lines, i.e. buried drains of the memory device. Two neighboring doped areas
24
define a channel, and the distance between the two neighboring doped areas
24
is defined as channel length. The ion implantation process
22
is performed perpendicular to the surface of the silicon substrate
10
using an arsenic (As) ion concentration of 1×10
14
~1×10
16
/cm
2
and having an energy ranging from 20 KeV to 200 KeV at room temperature.
As shown in
FIG. 3
, an ion implantation process with a first oblique angle
26
is performed to form a P-type pocket doped area
28
on one side of each doped area
24
. Then, as shown in
FIG. 4
, an ion implantation process with a second oblique angle
27
is performed to form a P-type pocket doped area
29
on the other side of each doped area
24
. The two ion implantation processes
26
and
27
have approximately the same ion implantation parameters.
The two ion implantation processes have a first oblique angle
26
and a second oblique angle
27
, the angles both ranging from 20° to 45°. Both implantation processes use BF
2
+
as a dopant, with a dosage ranging from 1×10
14
/cm
2
to 1×10
16
/cm
2
, and an energy ranging from 20 KeV to 150 KeV. Under these parameters, the BF
2
+
dopants mostly concentrate in the silicon substrate
10
to a depth of about 1000 Angstroms (Å) under the channel.
The advantage of forming P-type doped areas
28
and
29
is that it provides a high electric field area on one side of the channel. The high electric field area can increase the speed of electrons passing through the channel during a programming process. In other words, electrons accelerated to higher speeds can obtain enough kinetic energy to pass through the oxide layer
12
into the silicon nitride layer
14
by way of collision or scattering, so as to improve programming efficiency.
Following, as shown in
FIG. 5
, a photoresist ashing process (or a photoresist stripping process) is performed to remove the photoresist layer
20
. The prior art method to remove the photoresist layer
20
is performed in a plasma processing chamber. The plasma processing generally comprises a top electrode, which is normally connected to an RF generator, and a bottom electrode, which is usually grounded. A mixed photoresist ashing gas comprising oxygen and helium is used to generate plasma so as to quickly clean away the photoresist layer
20
.
Then, as shown in
FIG. 6
, a thermal oxidation method with a temperature of 900° C.~1150° C. is used to form a field oxide layer
32
on a top surface of the bit lines
24
so as to separate each silicon nitride layer
14
. Finally, a doped polysilicon layer
34
is deposited and functions as a word line. The dopants implanted into the silicon substrate
10
previously, including the dopants in the doped areas
24
,
28
and
29
, can be activated during the formation of the field oxide layer
32
.
To improve programming efficiency, it is better to distribute the highest concentration of dopants in the P-type doped areas
28
and
29
near the surface of the silicon substrate
10
, at a depth less than 500 Angstroms (Å). The above-mentioned prior art method for manufacturing NROM performs two ion implantation processes, using BF
2
+
as dopants, at oblique angles
26
and
27
, leading to the following problems. Because boron ions have a high diffusibility, the P-type doped areas
28
and
29
formed by the prior art method have a deep junction. Furthermore, electron secondary injection occurs to form an electron tail and a wider charge distribution. Therefore, electric holes cannot completely recombine with electrons in the subsequent operation of erase state, resulting incomplete erasing or long erasing time.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a method of preventing electron secondary injection in the pocket implantation process of a nitride read only memory (NROM).
The present invention provides a method to provide an NROM comprising an ONO layer formed on a silicon substrate. A plurality of bit line masks arranged in a column is formed on the surface of the ONO layer. A plurality of N-type bit lines is formed in the region of the substrate not covered by the bit line masks. A pocket implantation process using Indium ions is performed, having an angle nearly parallel to the ONO layer. The process implants to the region of the substrate not covered by the bit line masks, forming a plurality of P-type ultra-shallow doped areas. The Indium ions in the ultra-shallow doped area are activated to form an ultra-shallow junction on the surface of the silicon substrate. The pocket implantation process is an ion implantation process using a low energy and a high dosage to prevent electron secondary injection during the pocket implantation process.
It is an advantage of the present invention that the method performs a pocket implantation process using Indium ions as dopants so as to eliminate electron secondary injection and facilitate faster programming and shorter erase time.
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Chang Kent Kuohua
Pan Samuel Cheng-Sheng
Everhart Caridad
Hsu Winston
Luu Chuong Anh
Macronix International Co. Ltd.
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