Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-09-16
1998-01-13
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438660, H01L 218238
Patent
active
057078963
ABSTRACT:
A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs on the same substrate by alternate photoresist masking and ion implantation. The self-aligned source/drain areas for the P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions that are implanted in the P-channel FET gate electrodes during the source/drain implant results in out-gassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which out-diffuses the fluorine atoms prior to depositing the ILD, and thereby prevents the formation of voids after the ILD is deposited and subsequent high-temperature process steps are performed.
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patent: 5567638 (1996-10-01), Lin et al.
S. Wolf, "Silicon Processing for the VLSI Era-Vo12" Lattice Press, Sunset Beach, CA, p. 398; (1990).
Chen Pei-Hung
Chiang An-Min
Wann Yeh-Jye
Yu Shau-Tsung
Ackerman Stephen B.
Chaudhari Chandra
Saile George O.
Taiwan Semiconductor Manuacturing Company, Ltd.
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