Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2002-04-09
2004-04-06
Kielin, Erik (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S624000, C438S626000, C438S633000, C438S786000
Reexamination Certificate
active
06716771
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of making semiconductor devices, in particular, those that include low-k or ultra low-k dielectric layers, which have hydrophobic surfaces when initially deposited.
BACKGROUND OF THE INVENTION
Semiconductor devices include metal layers that are insulated from each other by dielectric layers. As device features shrink, reducing the distance between the metal layers and between metal lines formed within each layer, capacitance increases. To address this problem, insulating materials that have a relatively low dielectric constant are being used in place of silicon dioxide to form the dielectric layer that separates the metal lines.
Conventional single or dual damascene processes may be used to form metal lines within such low-k dielectric layers, e.g., to generate the structure
100
shown in
FIG. 1
b
.
FIG. 1
a
represents a cross-section of that structure prior to a polishing operation. In that figure, structure
100
includes substrate
101
, upon which is formed low-k dielectric layer
102
. After a trench has been etched into low-k dielectric layer
102
, barrier layer
103
is deposited. In addition to lining the trench, barrier layer
103
extends across surface
104
of low-k dielectric layer
102
. Conductive layer
105
, which may comprise copper, fills the trench and covers barrier layer
103
, where that layer rests on top of surface
104
.
After forming the
FIG. 1
a
structure, the excess material deposited on surface
104
must be removed, e.g., by using a conventional chemical mechanical polishing (“CMP”) process. Such a CMP operation may generate a structure in which barrier layer
103
and copper layer
105
remain within the trench only—as shown in FIG. 1
b
. Many commercially available rotary and orbital polishers may be used to perform such a CMP step. One example is the Reflexion™ 300 mm CMP system, which is available from Applied Materials, Inc.
After the CMP operation, structure
100
may be covered with thousands of slurry particles that must be removed, along with various metal contaminants. To remove those materials, structure
100
may be subjected to a series of cleaning and scrubbing steps. Many commercially available tools, e.g., the Reflexion system mentioned above, integrate CMP modules with a number of cleaning modules that perform those cleaning and scrubbing functions.
Certain materials that may be used to form low-k dielectric layers (e.g., carbon doped oxides) are hydrophobic. When processing a semiconductor wafer, which is covered by such a hydrophobic layer, through a tool's post-CMP cleaning modules, water drains off the wafer as it is moved from one module to the next. Any remaining water droplets may migrate to the interface between the conductive layer and the low-k dielectric layer. As those droplets shrink, the concentration of corrosive chemicals present in them may rise significantly. When the conductive layer includes copper, such highly concentrated droplets may corrode the copper. In addition, such rapid water loss may leave a significant amount of organic residue, which may render it difficult to bond the low-k dielectric layer to subsequently deposited materials.
Accordingly, there is a need for an improved process for making a semiconductor device that includes a hydrophobic dielectric layer. There is a need for such a process that converts a hydrophobic surface of such a layer to a hydrophilic one in a relatively simple way. There is a need for such a process that may be used during a post-CMP cleaning operation to reduce corrosion and improve adhesion characteristics. The method of the present invention provides such a process.
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Wolf, et al. Silicon Processing for the VLSI Era, vol. 1-Process Technology, 2nd ed., Lattice Press: Sunset Beach CA, 2000, pp. 761-764, 797-801.
Buehler Mark F.
Fredrickson Larry R.
Intel Corporation
Kielin Erik
Seeley Mark V.
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