Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-02
2002-06-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S186000, C700S114000, C700S096000, C700S097000, C700S121000, C700S182000, C438S599000, C438S614000, C257S676000, C257S777000, C257S784000, C257S786000
Reexamination Certificate
active
06405357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for designing a semiconductor die and, more particularly, to a method for determining positions of bond pads of the semiconductor die.
2. Description of the Related Art
One stage of integrated circuit design involves determining where bond pads are to be located on the die or chip. The placement of bond pads is not a trivial design task. For example, capabilities of manufacturing processes must be taken into account. When a die is designed to use wire bonding (as opposed to tape automated bonding or flip chip bonding), the placement of bond pads is of critical importance.
Several techniques exist for determining appropriate positions for bond pads in dies which are to be wire bonded around the die periphery. One of the simplest and most prevalent techniques is to simply divide the available perimeter of the semiconductor die by the required number of bond pads. The result is a bond pad configuration having a constant pad pitch (where pitch is the distance from the center of one bond pad to the center of an immediately adjacent pad) around the entire die periphery. A problem with this method is that the “wire pitch” (the actual pitch between immediately adjacent bonding wires) is not constant around the die periphery, unless all the wires are parallel. Instead, the wire pitch decreases as the die corners are approached because the contact pads (such as inner lead portions of a lead frame or fingers of a substrate) to which the bonding wires are eventually bonded are at a larger pitch than the bond pads. This effect is illustrated in FIG.
1
. In
FIG. 1
, P equals the constant bond pad pitch and P′ equals the wire pitch. As bonding wires
10
approach corners of a semiconductor die
12
, an angle &thgr; increases due to an increasing pitch of fingers
14
. As a result, the wire pitch (P′) is gradually reduced according to the equation: P′
x
=P*Cos(&thgr;
x
). The wire pitch is an important parameter because this distance effects the ability of a wire bonding tool to make bonds without the capillary of the tool disturbing previously made wire bonds. Use of constant pitch bond pad layout may not lead to a layout suitable for manufacturing if the wire pitch becomes too small.
A prior art improvement over the traditional single row of bond pads having constant pad pitches is the use of constant wire pitches as taught in U.S. Pat. No. 5,498,767. A constant wire pitch device maintains a constant wire pitch, while the pad pitch between adjacent pads varies, thereby allowing a wire bonding tool to make bonds without the capillary of the tool disturbing previously made wire bonds. A constant wire pitch semiconductor die characterizes in that the pad pitch is diminished from a maximum at the corners to a minimum at the die centerlines. However, a problem with the method taught in U.S. Pat. No. 5,498,767 is that it fails to consider effect of capillary tool and error in wire bonding process. Further, the minimum wire pitch required for bond pads with different functions differ from one another.
Accordingly, the present invention seeks to provide a method for determining positions of bond pads of a semiconductor die which overcomes, or at least reduces the abovementioned problems of the prior art.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a method for positioning bond pads in a semiconductor die using function orientation pad pitch to significantly reduce unnecessary pad spacing such that smaller die sizes are achievable.
It is another object of the present invention to provide a method for positioning bond pads in a semiconductor die which further takes into account effect of capillary tool and errors in wire bonding process which may be imposed upon bond pad placement, thereby making the operation of wire bonding more suitable for manufacturing.
The method according to a preferred embodiment of the present invention for positioning bond pads along an edge of a semiconductor die from a die corner comprises the steps of (I) setting parameters including (a) setting a baseline pad pitch to a first value, (b) setting a first pad position equal to a first pad value and (c) providing a focal point (in the present invention, the wire directions are assumed to be parallel to the lines that the pad centers form with an optimized focal point; the wires at the die corners are assumed to be approximately in line with the direction of the die diagonals); (II) determining a first angle between a first line through a center of the first pad position and the focal point and a second line through a center of the semiconductor die and normal to the edge; (III) determining a first pad spacing increment value equal to the first value divided by a cosine of the first angle; (IV) setting a second pad position equal to a second pad value, wherein the second pad value at least equals the first pad value plus the first value if both of the first bond pad and the second bond pad are ground pad or power pad with the same potential, else the second pad value at least equals the first pad value plus the first pad spacing increment value; and (V) using the first and second pad values to respectively position a first bond pad and a second bond pad along the edge of the semiconductor die. Beginning from the bond pad closest to the die corner, optimized positions of bond pads can be determined by repeating steps I to V. When two adjacent bond pads are both ground pad or power pad with the same potential, the pad pitch between them can be always set as the baseline pad pitch even they are positioned approaching to the die corner. This is because there is nearly no influence even two ground wires (or power wires) get short circuit. Therefore, the present invention significantly reduce unnecessary pad spacing such that smaller die sizes are achievable.
The method for positioning bond pads in accordance with the present invention may further consider the effect of capillary tool and manufacturing error imposed upon bond pad placement. At this time, the step of setting parameters further includes (d) setting an effective radius of capillary tool to a second value, and (e) setting an overall estimated error of wire bonding to a third pad value. They can be used to determine a fourth value equal to the second value plus the third value, and then determine a second pad spacing increment value equal to the fourth value divided by a cosine of the first angle. If the wire bonding of the second bond pad is designed to be conducted before the wire bonding of the first bond pad, the second pad value must at least equal the first pad value plus the second pad spacing increment value. Accordingly, by further considering the effect of capillary tool and manufacturing error as described above, the method of present invention significantly reduce the occurrence of the problem that capillary tool interferes or contacts previously made wire bonds.
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Chao Te Tsung
Fang Hui Chin
Advanced Semiconductor Engineering Inc.
Kik Phallaka
Smith Matthew
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